Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Methods for forming a semiconductor device including fine patterns
US9099403B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9099403-B2 |
| Application number | US-201314098897-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 6, 2013 |
| Priority date | Dec 6, 2012 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Abstract
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Methods for forming a semiconductor device including fine patterns are provided. The method may include forming a mask layer including first holes spaced apart from each other in a first direction and a second direction. The method may also include forming local mask patterns on the mask layer and forming a sacrificial layer on the mask layer filling the first holes and surrounding the local mask patterns. The local mask patterns may be offset from the first holes in the first direction and the second direction. The method may further include removing the local mask patterns to form openings in the sacrificial layer exposing the mask layer and etching the mask layer through the opening to form second holes in the mask layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for forming a semiconductor device, the method comprising: forming a hard mask layer comprising a plurality of first holes spaced apart from each other in a first direction and a second direction on a substrate; forming a plurality of local mask patterns on the hard mask layer, wherein the plurality of local mask patterns are offset from the plurality of first holes in the first direction and the second direction; forming a sacrificial layer on…
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Classifications
Electricity · mapped topic
- H10P50/73Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9099403B2 cover?
- Methods for forming a semiconductor device including fine patterns are provided. The method may include forming a mask layer including first holes spaced apart from each other in a first direction and a second direction. The method may also include forming local mask patterns on the mask layer and forming a sacrificial layer on the mask layer filling the first holes and surrounding the local ma…
- Who is the assignee on this patent?
- Kim Nam-Gun, Jang Kyungho, Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P50/73. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).