Semiconductor device

US9099362B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9099362-B2
Application numberUS-201213544513-A
CountryUS
Kind codeB2
Filing dateJul 9, 2012
Priority dateNov 9, 2000
Publication dateAug 4, 2015
Grant dateAug 4, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a conventional analog buffer circuit composed of polycrystalline semiconductor TFTs, a variation in the output is large. Thus, a measure such as to provide a correction circuit has been taken. However, there has been such a problem that a circuit and driver operation are complicated. Therefore, a gate length and a gate width of a TFT composing an analog buffer circuit is set to be larger. Also, a multi-gate structure is adopted thereto. In addition, the arrangement of channel regions is devised. Thus, the analog buffer circuit having a small variation is obtained without using a correction circuit, and a semiconductor device having a small variation can be provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a driver circuit comprising: a first channel region; a second channel region; a third channel region adjacent to the first and the second channel region; a fourth channel region adjacent to the first and the second channel region; a fifth channel region; a first gate electrode overlapping with the first channel region and the second channel region, wherein the first gate electrode includes a first slit overlappi…

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What does patent US9099362B2 cover?
In a conventional analog buffer circuit composed of polycrystalline semiconductor TFTs, a variation in the output is large. Thus, a measure such as to provide a correction circuit has been taken. However, there has been such a problem that a circuit and driver operation are complicated. Therefore, a gate length and a gate width of a TFT composing an analog buffer circuit is set to be larger. Al…
Who is the assignee on this patent?
Koyama Jun, Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D86/0251. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).