Semiconductor device and manufacturing method thereof

US9099323B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9099323-B2
Application numberUS-201113244054-A
CountryUS
Kind codeB2
Filing dateSep 23, 2011
Priority dateJun 9, 2011
Publication dateAug 4, 2015
Grant dateAug 4, 2015

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A Si-on-half-insulator device and its manufacturing method are disclosed in this invention. In one embodiment, a horizontal insulating layer located below at least one of the source and drain regions is realized to reduce junction capacitance. In another embodiment, a horizontal insulating layer located below at least one of the source and drain regions and a vertical insulating layer located below at least one side surface of the gate are realized. The additional vertical insulating layer can reduce punch leakage. Further, a method of manufacturing the above semiconductor device is also disclosed, wherein the horizontal and vertical insulating layers are formed using an additional layer of epitaxially grown semiconductor material and isolating trenches.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of manufacturing semiconductor device, comprising the following steps: providing a substrate of a first semiconductor material, forming a protrusion with an expected height on the substrate, and providing a cap-shaped mask covering the top and sidewalls of the protrusion; growing a layer of second semiconductor material on the surfaces of the substrate at opposite sides of the protrusion; removing a portion of the cap-shaped mask to expose…

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What does patent US9099323B2 cover?
A Si-on-half-insulator device and its manufacturing method are disclosed in this invention. In one embodiment, a horizontal insulating layer located below at least one of the source and drain regions is realized to reduce junction capacitance. In another embodiment, a horizontal insulating layer located below at least one of the source and drain regions and a vertical insulating layer located b…
Who is the assignee on this patent?
Liu Jinhua, Semiconductor Mfg Int Beijing
What technology area does this patent fall under?
Primary CPC classification H10D30/0227. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).