Method for fabricating power semiconductor device

Patent metadata

Field	Value
Publication number	US-9099321-B2
Application number	US-201313920033-A
Country	US
Kind code	B2
Filing date	Jun 17, 2013
Priority date	Apr 11, 2013
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

A substrate having thereon an epitaxial layer is provided. A hard mask having a first opening is formed on the epitaxial layer. A first trench is etched into the epitaxial layer through the first opening. The hard mask is trimmed to widen the first opening to a second opening. An upper corner portion of the first trench is revealed. A dopant layer is filled into the first trench. The dopants are driven into the epitaxial layer to form a doped region within the first trench. The doped region includes a first region adjacent to the surface of the first trench and a second region farther from the surface. The entire dopant layer is then etched and the epitaxial layer within the first region is also etched away to form a second trench.

First claim

What is claimed is:

1. A method for fabricating a power semiconductor device, comprising:
providing a semiconductor substrate;
forming an epitaxial layer on the semiconductor substrate;
forming a hard mask layer on the epitaxial layer;
forming at least one first opening in the hard mask layer;
etching the epitaxial layer through the first opening to form at least one first trench;
trimming the hard mask layer to enlarge the first opening to a second opening such that upp…

Assignees

• Anpec Electronics Corp

Inventors

• Lin Yung-Fa

Classifications

• H10P50/695

  Electricity · mapped topic

• H10P32/1414

  Electricity · mapped topic

• H10P32/171

  Electricity · mapped topic

• H10P32/00 Primary

  Electricity · mapped topic

• H10P30/20

  Electricity · mapped topic