Semiconductor devices including spacers on sidewalls of conductive lines and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9099302-B2
Application number	US-201414514207-A
Country	US
Kind code	B2
Filing date	Oct 14, 2014
Priority date	Jul 30, 2012
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

Semiconductor devices are provided that include spacers on sidewalls of conductive lines, as well as methods for manufacturing the same. A method for manufacturing a semiconductor device includes forming bit lines on a semiconductor substrate. Triple-layered bit line spacers are formed on respective sidewalls of the bit lines. An interlayer insulation layer is formed on the bit lines and the triple-layered bit line spacers. Storage node contact plugs that penetrate the interlayer insulation layer are formed between the bit lines. Portions of the triple-layered bit line spacers are etched to form recessed regions. An insulation layer is formed on the substrate including the recessed regions. Storage node electrodes electrically connected to the storage node contact plugs are formed.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming bit lines on a semiconductor substrate;
forming triple-layered bit line spacers on respective ones of sidewalls of the bit lines;
forming an interlayer insulation layer on the bit lines and the triple-layered bit line spacers;
forming storage node contact plugs that penetrate the interlayer insulation layer between the bit lines;
etching portions of the triple-layered bi…

Assignees

• Sk Hynix Inc

Inventors

• Lee Jong Pil

Classifications

• H10P14/60

  Electricity · mapped topic

• H10W20/077

  Electricity · mapped topic

• H10W20/075

  Electricity · mapped topic

• H10W99/00

  Electricity · mapped topic

• H10W70/635

  Electricity · mapped topic