Power failure tolerant cryptographic erase

US9092370B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9092370-B2
Application numberUS-201314135256-A
CountryUS
Kind codeB2
Filing dateDec 19, 2013
Priority dateDec 3, 2013
Publication dateJul 28, 2015
Grant dateJul 28, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of cryptographically erasing data in a storage device, at a controller of the storage device, the storage device having a first encryption key established as a current encryption key prior to performance of the method, the method comprising: updating a durably stored progress indicator to indicate a first stage; performing a set of first stage operations, including: obtaining a second encryption key; in accordance with a determination that a power fail condition did not occur while the progress indicator indicates the first stage: updating the progress indicator to indicate a second stage; performing a set of second stage operations, including: storing, in a first set of memory blocks on the storage device, a first set of metadata corresponding to the first set of memory blocks, encrypted using the second encryption key; and storing, in the first set of memory blocks, a second set of metadata corresponding to a second set of memory blocks on the storage device, encrypted using the second encryption key; wherein the second set of memory blocks does not comprise any memory block in the first set of memory blocks; and, in accordance with a determination that a power fail condition did not occur while the progress-counter indicates the second stage: updating the progress indicator to indicate a third stage; performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key; and subsequent to storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key, setting the second encryption key as the current encryption key for the plurality of memory blocks. 2. The method of claim 1 , further comprising: in accordance with a determination that a power fail condition occurred while the progress indicator indicates the first stage, repeating performance of the first stage operations. 3. The method of claim 1 , further comprising: in accordance with a determination that a power fail condition occurred while the progress indicator indicates the second stage, repeating performance of the second stage operations. 4. The method of claim 1 , further comprising: in accordance with a determination that a power fail condition occurred while the progress indicator indicates the third stage, repeating performance of the third stage operations. 5. The method of claim 1 , including, prior to storing, in the first set of memory blocks, the second set of metadata encrypted using the second encryption key: decrypting the second set of metadata using the first encryption key; and encrypting the second set of metadata using the second encryption key. 6. The method of claim 1 , wherein the second stage operations include durably storing information identifying the first set of memory blocks. 7. The method of claim 1 , wherein setting the second encryption key as the current encryption key for the plurality of memory blocks includes rendering the first encryption key unusable. 8. The method of claim 1 , wherein obtaining a second encryption key includes: encrypting the second encryption key; and durably storing the encrypted second encryption key. 9. The method of claim 1 , including selecting the first set of memory blocks from a plurality of memory blocks on the storage device by selecting memory blocks with the fewest erase cycles, memory blocks with fastest read or write times, or a first available set of memory blocks. 10. The method of claim 1 , further comprising, subsequent to storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key, erasing at least a portion of the first set of memory blocks and storing, in the erased portion of the first set of memory blocks, the first set of metadata encrypted using the second encryption key. 11. A method of cryptographically erasing data in a storage device having a first set of memory blocks and a second set of memory blocks, wherein the second set of memory blocks does not comprise any memory block in the first set of memory blocks, the first set of memory blocks storing a first set of metadata and the second set of memory blocks storing a second set of metadata, the storage device further having a first encryption key established as a current encryption key, to encrypt metadata and data, if any, in at least the first and second sets of memory blocks, prior to performance of the method, the method comprising: performing a power-failure tolerant cryptographic erase operation, including: obtaining and storing a second encryption key; storing, in the first set of memory blocks, the second set of metadata encrypted with the second encryption key; subsequent to storing, in the first set of memory blocks, the second set of metadata encrypted with the second encryption key, storing the second set of metadata encrypted with the second encryption key at corresponding locations in the second set of memory blocks; storing the first set of metadata encrypted with the second encryption key in the first set of memory blocks; and establishing the second encryption key as the current encryption key to encrypt metadata and data, if any, in at least the first and second sets of memory blocks, wherein performing the cryptographic erase operation further comprises: storing in non-volatile memory a progress indicator that indicates a stage of the cryptographic erase operation, and updating the progress indicator upon completion of each stage of a predefined set of stages of the cryptographic erase operation; determining whether a power failure has occurred while performing the cryptographic erase operation; and, in accordance with a determination that a power failure has occurred while performing the cryptographic erase operation, resuming performance of the cryptographic erase operation at a stage corresponding to a value of the progress indicator. 12. A storage device, comprising: an interface for coupling the storage device to a host system; and a controller having one or more processors, the controller configured to: update a durably stored progress indicator to indicate a first stage; perform a set of first stage operations, including: obtain a second encryption key; in accordance with a determination that a power fail condition did not occur while the progress indicator indicates the first stage: update the progress indicator to indicate a second stage; perform a set of second stage operations, including: store, in a first set of memory blocks on the storage device, a first set of metadata corresponding to the first set of memory blocks, encrypted using the second encryption key; and store, in the first set of memory blocks, a second set of metadata corresponding to a second set of memory blocks on the storage device, encrypted using the second encryption key, wherein the second set of memory blocks does not comprise any memory block in the first set of memory blocks; and, in accordance with a determination that a power fail condition did not occur while the progress-counter indicates the second stage: update the progress indicator to indicate a third stage; perform a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key; and, subsequent to storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key, set the second encryption key as the current encryption key for the plurality of memory blocks. 13

Assignees

Inventors

Classifications

  • in relation to content · CPC title

  • Resetting or repowering · CPC title

  • Protecting data · CPC title

  • Clearing memory, e.g. to prevent the data from being stolen · CPC title

  • Multiple device management, e.g. distributing data over multiple flash devices · CPC title

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Frequently asked questions

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What does patent US9092370B2 cover?
The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. …
Who is the assignee on this patent?
Sandisk Entpr Ip Llc
What technology area does this patent fall under?
Primary CPC classification G06F12/1408. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).