Fixed voltage generating circuit

Patent metadata

Field	Value
Publication number	US-9088252-B2
Application number	US-201414197220-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Mar 5, 2013
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

A fixed voltage generating circuit includes a current mirror, a differential pair, and a resistor coupled to the current mirror. A node of the resistor is coupled to a voltage source. The differential pair includes two resistors coupled to the voltage source to enable the differential pair outputting a stable output voltage.

First claim

What is claimed is:

1. A fixed voltage generating circuit comprising:
a first resistor having a first end and a second end, the second end of the first resistor being coupled to a voltage source;
a first transistor having a first end, a second end, and a control end, the control end of the first transistor being coupled to the first end of the first resistor, the first end of the first transistor being coupled to a ground node, and the second end of the first transistor being coupled to the control end of the first transistor;
a second transistor having a first end, a second end, and a control end, the control end of the second transistor being coupled to the control end of the first transistor, and the first end of the second transistor being coupled to the ground node;
a third transistor having a first end, a second end, and a control end, the control end of the third transistor being configured to receive a first differential voltage, and the first end of the third transistor being coupled to the second end of the second transistor;
a fourth transistor having a first end, a second end, and a control end, the control end of the fourth transistor being configured to receive a second differential voltage, and the first end of the fourth transistor being coupled to the second end of the second transistor;
a second resistor having a first end and a second end, the first end of the second resistor being coupled to the second end of the third transistor, and the second end of the second resistor being coupled to the voltage source; and
a third resistor having a first end and a second end, the first end of the third resistor being coupled to the second end of the fourth transistor, and the second end of the third resistor being coupled to the voltage source;
wherein a resistance of the second resistor and a resistance of the third resistor are related to a resistance of the first resistor.

2. The fixed voltage generating circuit of claim 1 , wherein an equivalent resistance of the second resistor and the third resistor is substantially equal to the resistance of the first resistor; and a size ratio of the first transistor and the second transistor is 1:1.

3. The fixed voltage generating circuit of claim 1 , wherein a current mirror is formed by the first transistor and the second transistor; and a size ratio of the first transistor and the second transistor is 1:N or N:1, wherein N is a positive integer.

4. The fixed voltage generating circuit of claim 1 further comprising n diodes coupled between the voltage source and the control end of the first transistor; wherein n is a positive integer.

5. The fixed voltage generating circuit of claim 4 , wherein the diodes are junction diodes, field effect transistors, or bipolar junction transistors.

6. The fixed voltage generating circuit of claim 1 , wherein the fixed voltage generating circuit is formed by a GaAs (GALLIUM ARSENIDE) process.

7. A fixed voltage generating circuit comprising:
a first resistor having a first end and a second end, the second end of the first resistor being coupled to a voltage source;
a first transistor having a first end, a second end, and a control end, the control end of the first transistor being coupled to the first end of the first resistor, the first end of the first transistor being coupled to a ground node, and the second end of the first transistor being coupled to the control end of the first transistor;
a second transistor having a first end, a second end, and a control end, the control end of the second transistor being coupled to the control end of the first transistor, and the first end of the second transistor being coupled to the ground node;
a third transistor having a first end, a second end, and a control end, the control end of the third transistor being configured to receive a first differential voltage, and the first end of the third transistor being coupled to the second end of the second transistor;
a fourth transistor having a first end, a second end, and a control end, the control end of the fourth transistor being configured to receive a second differential voltage, and the first end of the fourth transistor being coupled to the second end of the second transistor;
a second resistor having a first end and a second end, the first end of the second resistor being coupled to the second end of the third transistor;
a third resistor having a first end and a second end, the first end of the third resistor being coupled to the second end of the fourth transistor; and
a fourth resistor having a first end and a second end, the first end of the fourth resistor being coupled to the second end of the second resistor and the second end of the third resistor, and the second end of the fourth resistor being coupled to the voltage source;
wherein a resistance of the second resistor, a resistance of the third resistor, and a resistance of the fourth resistor are related to a resistance of the first resistor.

8. The fixed voltage generating circuit of claim 7 , wherein an equivalent resistance of the second resistor, the third resistor, and the fourth resistor is substantially equal to the resistance of the first resistor; and a size ratio of the first transistor and the second transistor is 1:1.

9. The fixed voltage generating circuit of claim 7 , wherein a current mirror is formed by the first transistor and the second transistor; and a size ratio of the first transistor and the second transistor is 1:N or N:1, wherein N is a positive integer.

10. The fixed voltage generating circuit of claim 7 further comprising n diodes coupled between the voltage source and the control end of the first transistor; wherein n is a positive integer.

11. The fixed voltage generating circuit of claim 10 , wherein the diodes are junction diodes, field effect transistors, or bipolar junction transistors.

12. The fixed voltage generating circuit of claim 7 , wherein the fixed voltage generating circuit is formed by a GaAs (GALLIUM ARSENIDE) process.

13. The fixed voltage generating circuit of claim 7 further comprising:
a fifth resistor coupled between the first end of the third transistor and the second end of the second transistor; and
a sixth resistor coupled between the first end of the fourth transistor and the second end of the second transistor.

14. The fixed voltage generating circuit of claim 13 further comprising n diodes coupled between the voltage source and the control end of the first transistor; wherein n is a positive integer.

15. A fixed voltage generating circuit comprising:
a first resistor having a first end and a second end, the second end of the first resistor being coupled to a voltage source;
a first transistor having a first end, a second end, and a control end, the control end of the first transistor being coupled to the first end of the first resistor, the first end of the first transistor being coupled to a ground node, and the second end of the first transistor being coupled to the control end of the first transistor;
a second transistor having a first end, a second end, and a control end, the control end of the second transistor being coupled to the control end of the first transistor, and the first end of the second transistor being coupled to the ground node;
a third transistor having a first end, a second end, and a control end, the control end of the third transistor being configured to receive a first differential voltage;
a fourth transistor having a first end, a second end, and a control end, the control end of the fourth transistor being configured to receive a second differential voltage;
a second

Assignees

• Richwave Technology Corp

Inventors

• Chen Chih-Sheng
• Chao Chuan-Jane

Classifications

• H03F3/45085 Primary

  Long tailed pairs (H03F3/45112, H03F3/45139 take precedence) · CPC title