Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer

Patent metadata

Field	Value
Publication number	US-9087918-B2
Application number	US-201414146095-A
Country	US
Kind code	B2
Filing date	Jan 2, 2014
Priority date	Nov 21, 2008
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

First claim

What is claimed is:

1. A process of forming an MOS transistor, comprising the steps of:
forming a dummy gate stack, wherein said dummy gate stack includes a gate dielectric layer, a gate work function metal layer and a dummy gate layer;
removing said dummy gate layer;
performing a low temperature oxidation process, such that said effective work function of said gate work function metal layer is increased to a value above 4.85 eV;
forming an oxygen diffusion barrier layer over said gate work function metal layer;
forming an oxygen getter layer over said gate work function metal layer;
performing a getter anneal process; and
forming a metal gate over said gate work function metal layer.

2. The process of claim 1 , in which said gate work function metal layer has an effective work function between 4.5 and 4.7 eV.

3. The process of claim 1 , in which said step of removing said dummy gate layer further includes the steps of:
forming a hard mask on a top surface of said dummy gate layer;
forming a gate photoresist pattern on a top surface of said hard mask, such that said gate photoresist pattern defines an area for a gate of said MOS transistor;
performing a gate etch process, said gate etch process further including the steps of:
removing said hard mask outside of said gate area of said MOS transistor;
removing said dummy gate layer outside of said gate area of said MOS transistor;
removing said gate work function metal layer outside of said gate area of said MOS transistor; and
removing said gate dielectric layer outside of said gate area of said MOS transistor;

forming a fill oxide layer on a top surface of said substrate and a top surface of said hard mask;
removing said fill oxide layer from said top surface of said hard mask in said gate area of said MOS transistor;
removing said hard mask in said gate area of said MOS transistor; and
removing said dummy gate layer in said gate area of said MOS transistor.

4. The process of claim 3 , wherein:
said hard mask is between 20 and 40 nanometers thick; and
a composition of said hard mask is selected from the group consisting of:
SiN,
SiON,
SiC,
SiOC,
SiCON, and
any combination thereof.

5. The process of claim 3 , in which said step of forming an oxygen diffusion barrier layer over said gate work function metal layer further includes the step of forming an etch stop layer on a top surface of said gate work function metal layer prior to forming said oxygen diffusion barrier layer.

6. The process of claim 5 , wherein:
said etch stop layer is between 2 and 10 nanometers thick; and
a composition of said etch stop layer is selected from the group consisting of:
TaN,
WN,
TiC,
TaC, and
WC.

7. The process of claim 6 , in which said step of forming a metal gate further includes the steps of:
removing said oxygen getter layer;
forming a metal fill gate layer over said gate work function metal layer and on a top surface of said fill oxide layer; and
removing said metal fill gate layer from said top surface of said fill oxide layer.

8. The process of claim 7 , wherein:
said MOS transistor is a PMOS transistor;
said gate work function metal layer includes oxygen atoms such that said oxygen atoms have a distribution of at least 1×10 15 atoms/cm 2 within 1 nanometer of said top surface of said gate dielectric layer; and
said gate work function metal layer has an effective work function above 4.85 eV.

9. The process of claim 7 , wherein:
said MOS transistor is a PMOS transistor;
said gate work function metal layer includes oxygen atoms such that said oxygen atoms have an average concentration between 1×10 18 atoms/cm 3 and 1×10 21 atoms/cm 3 ; and
said gate work function metal layer has an effective work function above 4.85 eV.

10. The process of claim 7 , wherein:
said MOS transistor is an NMOS transistor;
said process of forming said transistor further includes the step of removing said oxygen diffusion barrier layer, such that said step of removing said oxygen diffusion barrier layer is performed after said step of forming an oxygen diffusion barrier layer and before said step of forming an oxygen getter layer;
said gate work function metal layer includes oxygen atoms such that said oxygen atoms have a distribution less than 1×10 13 oxygen atoms/cm 2 within 1 nanometer of said top surface of said gate dielectric layer;
said gate work function metal layer includes metal atoms from said oxygen getter layer such that said metal atoms have a distribution of at least 1×10 13 atoms/cm 2 within 1 nanometer of said top surface of said gate dielectric layer; and
said gate work function metal layer has an effective work function below 4.25 eV.

11. The process of claim 1 , wherein a composition of said gate dielectric layer is selected from the group consisting of:
SiO x ,
Si 3 N 4 ,
SiON,
Al 2 O 3 ,
AlON,
HfO,
HfSiO,
HfSiON,
ZrO,
ZrSiO,
ZrSiON,
nitridated SiO x ,
nitridated Al 2 O 3 ,
nitridated HfO,
nitridated HfSiO,
nitridated ZrO,
nitridated ZrSiO, and
any combination thereof.

12. The process of claim 1 , wherein:
said gate work function metal layer is between 1 and 10 nanometers thick; and
said gate work function metal layer includes a metal selected from the group consisting of:
TiN,
TaN, and
TaC.

13. The process of claim 1 , wherein said step of performing a low temperature oxidation process further includes the step of exposing said gate work function metal layer to a steam ambient between 300° C. and 600° C. for 10 seconds to 30 minutes.

14. The process of claim 1 , wherein said step of performing a low temperature oxidation process further includes the step of exposing said gate work function metal layer to a plasma containing oxygen and hydrogen at a temperature up to 500° C.

15. The process of claim 1 , wherein said step of performing a low temperature oxidation process further includes the step of anodizing said gate work function metal layer.

16. The process of claim 1 , wherein said step of performing a low temperature oxidation process further includes the step of exposing said gate work function metal layer to dry ambient containing an oxidizing component at a temperature between 300° C. and 700° C.

17. The process of claim 16 , wherein said oxidizing component is selected from the group consisting of:
O 2 ,
O 3 ,
NO,
NO 2 , and
any combination thereof.

18. The process of claim 1 , wherein said step of performing a low temperature oxidation process further includes the step of exposing said gate work function metal layer to H 2 O containing dissolved ozone.

19. The process of claim 1 , wherein said oxygen diffusion barrier layer is more than 10 nanometers thick.

20. The process of claim 1 , wherein a composition of said oxygen getter layer is selected from the group consisting of:
titanium,
hafnium,
zirconium,
tantalum,
aluminum,
cerium, and
lanthanum.

21. A process of forming an integrated circuit, comprising the steps of:
forming a dummy PMOS gate stack and a dummy NMOS gate stack, wherein said dummy PMOS gate stack includes a PMOS gate dielectric layer, a PMOS gate work function metal layer and a PMOS dummy gate layer, and said dummy NMOS gate stack includes a NMOS gate dielectric layer, a NMOS gate work function metal layer and a NMOS dummy gate layer;
removing said PMOS dummy gate layer and said NMOS dummy gate layer;
performing a low temperature oxidation process, such that said effective work

Assignees

• Texas Instruments Inc

Inventors

• Chambers James Joseph
• Niimi Hiroaki

Classifications

• H10P36/03

  within silicon bodies · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title