Device and method for forming sharp extension region with controllable junction depth and lateral overlap

Patent metadata

Field	Value
Publication number	US-9087772-B2
Application number	US-201213611387-A
Country	US
Kind code	B2
Filing date	Sep 12, 2012
Priority date	Apr 5, 2012
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

A method for forming a semiconductor device includes forming a gate stack on a monocrystalline substrate. A surface of the substrate adjacent to the gate stack and below a portion of the gate stack is amorphorized. The surface is etched to selectively remove a thickness of amorphorized portions to form undercuts below the gate stack. A layer is epitaxially grown in the thickness and the undercuts to form an extension region for the semiconductor device. Devices are also provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a gate electrode formed on a monocrystalline substrate over a channel region;
extension diffusion layers formed by crystal growth on top of a surface of the monocrystalline substrate on opposing sides of the channel region, each extension diffusion layer having a portion extending into an undercut formed in an implantation region underneath the gate electrode, wherein the undercut is angled such that a bottom surface of bottom portions of each extension diffusion layer extends horizontally farther underneath the gate electrode than top portions of the extension diffusion layer; and
source and drain diffusion regions formed in contact with the extension diffusion layers.

2. The semiconductor device as recited in claim 1 , wherein the extension diffusion layers includes a crystal structure formed on top of the surface of the monocrystalline substrate by epitaxial growth.

3. The semiconductor device as recited in claim 1 , wherein source and drain diffusion regions are formed below the extension diffusion layers in the monocrystalline substrate.

4. The semiconductor device as recited in claim 1 , wherein source and drain diffusion regions include raised regions formed on the extension diffusion layers.

5. The semiconductor device as recited in claim 1 , wherein the extension diffusion layers include a thickness of about 10 nm.

6. The semiconductor device as recited in claim 1 , wherein the undercut is angled between about 5 and about 20 degrees with respect to the vertical direction of the gate electrode.

Assignees

• Lauer Isaac
• Leobandung Effendi
• Shahidi Ghavam G
• IBM

Inventors

• Lauer Isaac
• Leobandung Effendi
• Shahidi Ghavam G

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10D30/0218

  having pocket halo regions selectively formed at the sides of the gates · CPC title