Clock signal timing-based noise suppression

Patent metadata

Field	Value
Publication number	US-9083354-B2
Application number	US-201313832708-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Jul 14, 2015
Grant date	Jul 14, 2015

Abstract

A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.

First claim

What is claimed is:

1. A method comprising:
generating one of a first clock signal and a second clock signal from the other clock signal, the first clock signal being configured to be used to synchronize an operation of an analog system and the second clock signal being configured to be used to synchronize an operation of a digital system; and
using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal,
wherein the generating comprises controlling a delay element of the digital system to regulate the timing based on the measurement of the timing by the phase detector to suppress noise in the analog system.

2. The method of claim 1 , wherein the controlling comprises controlling a delay of a delay element of a locked loop circuit in response to a measurement provided by a phase detector of the locked loop circuit.

3. The method of claim 1 , further comprising:
sampling an analog signal in the analog system in response to the first clock signal.

4. The method of claim 1 , further comprising:
generating the second clock signal from the first clock signal,
wherein the timing is regulated to suppress a noise in the analog system produced due to a coupling of the first and second clock signals.

5. The method of claim 1 , wherein using the phase detector to measure the timing comprises:
delaying the first clock signal using a plurality of delay elements of the analog system to generate a plurality of delayed first clock signals; and
using a signal synchronized to the second clock signal to trigger sampling of the plurality of delayed first clock signals to generate a plurality of samples collectively representing the timing.

6. The method of claim 5 , wherein the plurality of samples represent a digital value indicative of the timing, and controlling the delay element comprises selectively increasing and decreasing the delay based at least in part on a comparison of the digital value to a reference value.

7. An apparatus comprising:
an analog system adapted to synchronize at least one operation to a first clock signal;
a digital system adapted to synchronize at least one operation to a second clock signal, wherein the first and second clock signals are electrically coupled together; and
a clock regulation circuit adapted to regulate a timing of the first clock signal relative to the second clock signal to control a noise contained in the first clock signal, the clock regulation circuit comprising:
a phase detector disposed in the analog system to measure a timing of the first clock signal relative to the second clock signal;
a controllable delay element disposed in the digital system; and
a controller to regulate a delay of the delay element to regulate the timing based on the measurement of the timing by the phase detector.

8. The apparatus of claim 7 , wherein the clock regulation circuit comprises a delay locked loop (DLL) circuit.

9. The apparatus of claim 7 , wherein the digital system comprises a clock generator to generate the first and second clock signals.

10. The apparatus of claim 7 , wherein the analog system comprises a sampling circuit to respond to the first clock signal.

11. The apparatus of claim 7 , wherein the phase detector comprises:
a plurality of delay elements to delay a signal representative of the first clock signal to generate a plurality of delayed clock signals; and
a plurality of samplers to sample the delayed clock signals in response to the second clock signal to generate an indication of the timing.

12. The apparatus of claim 11 , wherein the controller is adapted to selectively adjust a delay of the delay element based at least in part on the indication generated by the samplers.

13. The apparatus of claim 12 , wherein the controller is adapted to selectively adjust a number of delay circuits forming a cascaded delay chain of the delay circuit based at least in part on the indication generated by the samplers.

14. An apparatus comprising:
an integrated circuit comprising a processor core, an analog component clocked by a first clock signal, a digital component clocked by a second clock signal, a clock generator module to generate the first clock signal and the second clock signal, and a locked loop circuit to control a relative timing of the first and second clock signals,
wherein the locked loop circuit comprises a controller disposed in a digital system of the integrated circuit, a delay circuit having a delay controllably adjusted by the locked loop circuit to control the timing and a phase detector disposed in an analog system of the integrated circuit that measures the timing, and
wherein the processor core is clocked by a clock signal synchronized to the second clock signal.

15. The apparatus of claim 14 , wherein the analog component is disposed in the analog system of the integrated circuit.

16. The apparatus of claim 14 , wherein the phase detector comprises:
a plurality of delay elements to generate a plurality of delayed analog clock signals in response to the first clock signal; and
a plurality of samplers to sample the delayed analog clock signals in response to the second signal to generate a value indicative of the timing.

17. The apparatus of claim 14 , wherein the delay circuit comprises a cascaded chain of selectively enabled delay elements.

18. The apparatus of claim 17 , wherein the locked loop circuit is adapted to selectively enable the delay elements based at least in part on the timing.

19. The apparatus of claim 14 , wherein the locked loop circuit comprises a delay locked loop (DLL) circuit.

Assignees

• Silicon Lab Inc

Inventors

• Islam Imranul
• Thomsen Axel
• Zavalney Paul I

Classifications

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• H03L7/0816 Primary

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title