Deep learning inference efficiency technology with early exit and speculative execution
US-2024104916-A1 · Mar 28, 2024 · US
Estimating system performance using an integrated circuit
US9081925B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9081925-B1 |
| Application number | US-201213398790-A |
| Country | US |
| Kind code | B1 |
| Filing date | Feb 16, 2012 |
| Priority date | Feb 16, 2012 |
| Publication date | Jul 14, 2015 |
| Grant date | Jul 14, 2015 |
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Abstract
Official abstract text for this publication.
A method of estimating performance of a design can include selecting a segment of the design for hardware emulation within an emulation system implemented within an integrated circuit. The emulation system can include a generic accelerator coupled to a processor of the integrated circuit. The method further can include modifying the design, using a processor of a host system, to invoke the generic accelerator in lieu of executing the selected segment within the processor of the emulation system during emulation.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of estimating performance of a design, the method comprising: selecting a segment of the design comprising a plurality of segments for hardware emulation; wherein the design is specified using processor-executable instructions; and modifying the design, using a processor of a host system, to invoke a generic accelerator of an emulation system in lieu of executing the selected segment within a processor of the emulation system; wherein at least…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F30/33Primary
Physics · mapped topic
- G06F11/261Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9081925B1 cover?
- A method of estimating performance of a design can include selecting a segment of the design for hardware emulation within an emulation system implemented within an integrated circuit. The emulation system can include a generic accelerator coupled to a processor of the integrated circuit. The method further can include modifying the design, using a processor of a host system, to invoke the gene…
- Who is the assignee on this patent?
- Schumacher Paul R, Schelle Graham F, Lysaght Patrick, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F30/33. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jul 14 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).