Extension of ADC dynamic range using post-processing logic

Patent metadata

Field	Value
Publication number	US-9077360-B2
Application number	US-201414194304-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Mar 1, 2013
Publication date	Jul 7, 2015
Grant date	Jul 7, 2015

Abstract

An apparatus, comprising: an analog to digital converter including: a clipping detector; and a post-processor, wherein the post processor generates synchronous values of clipped data based on non-clipped values of non-clipped data.

First claim

What is claimed is:

1. An apparatus, comprising:
an analog to digital converter including:
a clipping detector; and

a post-processor, wherein the post processor generates synchronous values of clipped data based on non-clipped values of non-clipped and non-compressed analog input signal,
wherein a programmable threshold is used in the clipping detector;
wherein the post processor employs an Akima algorithm, and
wherein the post processor further comprising means for assuming a Third Order Polynomial between the two closest asynchronous sample points surrounding the desired synchronous output sample point.

2. The apparatus of claim 1 , further comprising a means for puncturing asynchronous samples that are not within three samples of any synchronous output sample point.

3. The apparatus of claim 2 , wherein the puncturing of asynchronous samples that are not within three samples of any synchronous output point, leading to less power than using all asynchronous samples.

4. The apparatus of claim 3 , wherein a calculation of wherein the puncturing of asynchronous samples that are not within three samples of any synchronous output point is computationally less intensive than using all asynchronous samples.

5. The apparatus of claim 1 , wherein the post processor employs a modified Akima algorithm.

6. The apparatus of claim 1 , wherein the post processor employs a least squares solver in conjunction with the modified Akima algorithm.

7. The apparatus of claim 1 , wherein the ADC is a synchronous converter other than a sigma-delta.

8. The apparatus of claim 1 , wherein the ADC is an asynchronous converter.

9. A method, comprising:
receiving in the ADC converter receives an analog signal,
using a synchronous (except Delta-Sigma) or asynchronous converter to generate the digital representation of the analog signal, {D},
determining if a clipping event has occurred;
detecting from the digital samples (and/or analog waveform) detect which samples, {C} were corrupted by a clipping event,
removing the corrupted samples {C} from the digital signal representation, {D}, and sending the remaining sample set, {SU} to the next step;
using {SU} with one the non-uniform to uniform resampling algorithms a output set of synchronous samples, {SS}, is generated., wherein the non-uniform to uniform resampling algorithm employs a Third Order Polynomial between the two closest asynchronous sample points surrounding the desired synchronous output sample point.

10. The method of claim 9 , further comprising selecting the non-uniform to uniform sampler from at least one of the three including: Akima/Modified Akima/Augmented Least Square Solved, and a polynomial interpolation.

11. The method of claim 10 , wherein the polynomial interpolation is a spline interpolation.

12. The method of claim 9 , further comprising determining if a synchronous sampler is used.

13. An apparatus, comprising:
An analog to digital converter including:
a clipping detector; and
a post-processor, wherein the post processor generates synchronous samples using an asynchronous to synchronous generator, selected from the group including at least one of:
an Akima algorithm;
a modified Akima algorithm; and
a least squares solution; and
a polynomial interpolation;

a means for selecting the non-uniform to uniform sampler from at least one of the three including: Akima/Modified Akima/Augmented Least Square Solved, and a polynomial interpolation; and
a means for puncturing asynchronous samples that are not within three samples of any synchronous point.

14. The apparatus of claim 13 , wherein the polynomial interpolation is a spline interpolation.

15. The method of claim 13 , wherein the polynomial interpolation is a spline interpolation.

Assignees

• Texas Instruments Inc

Inventors

• Dasgupta Udayan
• Thiagarajan Ganesan
• Gopinathan Venugopal

Classifications

• H03M1/1265

  Non-uniform sampling · CPC title

• H03M1/36

  simultaneously only, i.e. parallel type · CPC title

• H03M1/0854

  of quantisation noise · CPC title

• H03M1/186

  in feedforward mode, i.e. by determining the range to be selected directly from the input signal · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title