Liquid crystal display having level shifter

Patent metadata

Field	Value
Publication number	US-9076399-B2
Application number	US-201313848883-A
Country	US
Kind code	B2
Filing date	Mar 22, 2013
Priority date	Mar 23, 2012
Publication date	Jul 7, 2015
Grant date	Jul 7, 2015

Abstract

A level shifter for a liquid crystal display is disclosed. The level shifter includes a pull-down transistor which includes a source terminal, to which the gate low voltage is supplied, and a drain terminal connected to an output terminal of the level shifter, and discharges a voltage of an output terminal of the level shifter, and an output stabilization circuit which is connected to a gate terminal of the pull-down transistor, controls a gate voltage of the pull-down transistor in the process of a power-on sequence, and discharges an output voltage of the level shifter.

First claim

What is claimed is:

1. A liquid crystal display comprising:
a display panel including data lines, gate lines crossing the data lines, and pixels arranged in a matrix form;
a level shifter outputting a start pulse and clock signals;
a shift register sequentially supplying a gate pulse to the gate lines in response to the start pulse and the clock signals received from the level shifter; and
a power integrated circuit (IC) sequentially outputting a gate low voltage, a logic power voltage, and a gate high voltage in the process of a power-on sequence,
the level shifter including:
a pull-down transistor configured to include a source terminal, to which the gate low voltage is supplied, and a drain terminal connected to an output terminal of the level shifter, the pull-down transistor discharging a voltage of the output terminal of the level shifter; and
an output stabilization circuit configured to be connected to a gate terminal of the pull-down transistor,
wherein the output stabilization circuit discharges an output voltage of the level shifter to the gate low voltage by controlling a gate voltage of the pull-down transistor to turn on the pull-down transistor before the gate high voltage is input to the level shifter in the process of the power-on sequence.

2. The liquid crystal display of claim 1 , wherein the output stabilization circuit includes:
a first resistor connected to a ground level voltage source;
a first diode connected between the first resistor and the source terminal of the pull-down transistor;
a second resistor connected between a node between the first resistor and the first diode and the gate terminal of the pull-down transistor; and
a second diode connected between the second resistor and the gate terminal of the pull-down transistor.

3. The liquid crystal display of claim 2 , wherein the first diode includes an anode connected to the source terminal of the pull-down transistor and a cathode connected to a node between the first and second resistors,
wherein the second diode includes a cathode connected to the gate terminal of the pull-down transistor and an anode connected to the second resistor.

4. The liquid crystal display of claim 1 , wherein the output stabilization circuit includes a switch supplying the logic power voltage to the gate terminal of the pull-down transistor in the process of the power-on sequence.

5. The liquid crystal display of claim 4 , wherein the switch of the output stabilization circuit includes a diode having a cathode connected to the gate terminal of the pull-down transistor and an anode connected to a second resistor.

6. The liquid crystal display of claim 1 , wherein the level shifter further includes a pull-up transistor having a source terminal, to which the gate high voltage is supplied, and a drain terminal connected to an output terminal of the level shifter, the pull-up transistor supplying the gate high voltage to the output terminal of the level shifter.

7. The liquid crystal display of claim 6 , wherein the pull-up transistor is implemented as a p-type metal oxide semiconductor field-effect transistor (MOSFET), and the pull-down transistor is implemented as an n-type MOSFET.

8. The liquid crystal display of claim 1 , wherein the output stabilization circuit increases the gate voltage of the pull-down transistor before the gate high voltage is input to the level shifter in the process of the power-on sequence.

9. A liquid crystal display comprising:
a display panel including data lines, gate lines crossing the data lines, and pixels arranged in a matrix form;
a level shifter outputting a start pulse and clock signals;
a shift register sequentially supplying a gate pulse to the gate lines in response to the start pulse and the clock signals received from the level shifter; and
a power integrated circuit (IC) sequentially outputting a gate low voltage, a logic power voltage, and a gate high voltage in the process of a power-on sequence,
the level shifter including:
a pull-down transistor including a source terminal, to which the gate low voltage is supplied, and a drain terminal connected to an output terminal of the level shifter, the pull-down transistor discharging a voltage of the output terminal of the level shifter; and
an output stabilization circuit which is connected to a gate terminal of the pull-down transistor, controls a gate voltage of the pull-down transistor in the process of the power-on sequence, and discharges an output voltage of the level shifter,
wherein the output stabilization circuit includes:
a first resistor connected to a ground level voltage source;
a first diode connected between the first resistor and the source terminal of the pull-down transistor;
a second resistor connected between a node between the first resistor and the first diode and the gate terminal of the pull-down transistor; and
a second diode connected between the second resistor and the gate terminal of the pull-down transistor.

10. The liquid crystal display of claim 9 , wherein the level shifter further includes a pull-up transistor having a source terminal, to which the gate high voltage is supplied, and a drain terminal connected to an output terminal of the level shifter, the pull-up transistor supplying the gate high voltage to the output terminal of the level shifter.

11. The liquid crystal display of claim 10 , wherein the pull-up transistor is implemented as a p-type metal oxide semiconductor field-effect transistor (MOSFET), and the pull-down transistor is implemented as an n-type MOSFET.

12. The liquid crystal display of claim 9 , wherein the output stabilization circuit increases the gate voltage of the pull-down transistor before the gate high voltage is input to the level shifter in the process of the power-on sequence.

13. A liquid crystal display comprising:
a display panel including data lines, gate lines crossing the data lines, and pixels arranged in a matrix form;
a level shifter outputting a start pulse and clock signals;
a shift register sequentially supplying a gate pulse to the gate lines in response to the start pulse and the clock signals received from the level shifter; and
a power integrated circuit (IC) sequentially outputting a gate low voltage, a logic power voltage, and a gate high voltage in the process of a power-on sequence,
the level shifter including:
a pull-down transistor including a source terminal, to which the gate low voltage is supplied, and a drain terminal connected to an output terminal of the level shifter, the pull-down transistor discharging a voltage of the output terminal of the level shifter; and
an output stabilization circuit which is connected to a gate terminal of the pull-down transistor, controls a gate voltage of the pull-down transistor in the process of the power-on sequence, and discharges an output voltage of the level shifter,
wherein the output stabilization circuit includes:
a first resistor connected to a ground level voltage source;
a first diode connected between the first resistor and the source terminal of the pull-down transistor;
a second resistor connected between a node between the first resistor and the first diode and the gate terminal of the pull-down transistor; and
a second diode connected between the second resistor and the gate terminal of the pull-down transistor,
wherein the first diode includes an anode connected to the source terminal of the pull-down transistor and a cathode connected to a node between the first and second resistors, and
wherein the second diode includes a cathode connected to the gate terminal of the pull-down transistor and an anode connected to the

Assignees

• Lg Display Co Ltd

Inventors

• Park Mingyu

Classifications

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title