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Information processing apparatus that detects startup error, method of controlling the same, and storage medium
US9075752B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9075752-B2 |
| Application number | US-201213461990-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 2, 2012 |
| Priority date | May 9, 2011 |
| Publication date | Jul 7, 2015 |
| Grant date | Jul 7, 2015 |
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Abstract
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An information processing apparatus which includes at least two controllers and is capable of positively detecting a startup error. Memory devices are connected to the controllers, respectively. A CPU of each controller accesses the memory device connected to the other controller via a bus bridge, identifies a startup stage to which the startup process has proceeded during the start of the self-controller, writes the identified startup stage as startup information into the memory device connected to the other controller, and detects whether or not an abnormality occurs during the startup of the other controller with reference to the startup information written into the memory device connected to the self-controller.
First claim
Opening claim text (preview).
What is claimed is: 1. An information processing apparatus that includes at least two controllers, each of which shares job processing, comprising: memory devices which are connected to the controllers, respectively; and an access unit for accessing from one of the controllers to one of said memory devices which is connected to the other of the controllers, wherein each of the at least two controllers comprises an identification unit, a writing unit, and an abnormality detecti…
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Physics · mapped topic
- G06F11/1417Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9075752B2 cover?
- An information processing apparatus which includes at least two controllers and is capable of positively detecting a startup error. Memory devices are connected to the controllers, respectively. A CPU of each controller accesses the memory device connected to the other controller via a bus bridge, identifies a startup stage to which the startup process has proceeded during the start of the self…
- Who is the assignee on this patent?
- Hamaguchi Jun, Canon Kk
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1417. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jul 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).