Memory system

Patent metadata

Field	Value
Publication number	US-9075740-B2
Application number	US-201414296001-A
Country	US
Kind code	B2
Filing date	Jun 4, 2014
Priority date	Mar 7, 2008
Publication date	Jul 7, 2015
Grant date	Jul 7, 2015

Abstract

A memory system ( 10 ) is disclosed, which comprises a flash-EEPROM nonvolatile memory ( 11 ) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory ( 13 ) that temporarily stores data of the flash-EEPROM nonvolatile memory ( 11 ), a control circuit ( 12, 14 ) that controls the flash-EEPROM nonvolatile memory ( 11 ) and the cache memory ( 13 ), and an interface circuit ( 16 ) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.

First claim

The invention claimed is:

1. A memory system comprising:
a nonvolatile memory comprising a plurality of storage areas each including memory portions that each store one of a first data item and a second data item;
a cache memory that temporarily stores data read from the nonvolatile memory;
a control circuit that controls the nonvolatile memory and the cache memory, the control circuit comprising a counter that is configured to count the number of the first data items; and
a…

Assignees

• Toshiba Kk

Inventors

• Nagadomi Yasushi
• Takashima Daisaburo
• Hatsuda Kosuke

Classifications

• G06F12/0246 Primary

  Physics · mapped topic

• G06F2212/7203

  Physics · mapped topic

• G11C16/102

  Physics · mapped topic

• G06F11/1016 Primary

  Physics · mapped topic

• G06F2212/7209

  Physics · mapped topic