Storage system and method of controlling data transfer in storage system

US9075729B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9075729-B2
Application numberUS-201213511888-A
CountryUS
Kind codeB2
Filing dateMay 16, 2012
Priority dateMay 16, 2012
Publication dateJul 7, 2015
Grant dateJul 7, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device.

First claim

Opening claim text (preview).

The invention claimed is: 1. A storage system comprising: a plurality of non-volatile storage devices for storing user data; and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host, wherein the controller includes a processor core circuit, a processor cache, a data transfer circuit, a drive interface circuit, and a primary storage device including a cache area for temporarily storing user data; wherein the processor cor…

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What does patent US9075729B2 cover?
An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing use…
Who is the assignee on this patent?
Okada Naoya, Takada Masanori, Hirayama Hiroshi, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F12/0868. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).