Deferred execution in a multi-thread safe system level modeling simulation

Patent metadata

Field	Value
Publication number	US-9075666-B2
Application number	US-201313971026-A
Country	US
Kind code	B2
Filing date	Aug 20, 2013
Priority date	Aug 20, 2013
Publication date	Jul 7, 2015
Grant date	Jul 7, 2015

Abstract

Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

First claim

What is claimed is:

1. A computer implemented method for multi-threaded system level modeling simulation (SLMS) of a target system on a host system, the method comprising:
beginning parallel execution of a plurality of SLMS processes via a plurality of threads, the SLMS processes representing functional behaviors of components within the target system;
during the parallel execution of the SLMS processes, detecting operations within the SLMS processes that access at least one sha…

Assignees

• Synopsys Inc

Inventors

• Janssen Jan M J
• Grötker Thorsten H
• Schumacher Christoph
• Leupers Rainer

Classifications

• G06F9/4881

  Physics · mapped topic

• G06F9/52 Primary

  Physics · mapped topic

• G06F9/5061

  Physics · mapped topic