Method of growing nitride semiconductor layer, nitride semiconductor device, and method of fabricating the same
US-2015380237-A1 · Dec 31, 2015 · US
III nitride semiconductor substrate, epitaxial substrate, and semiconductor device
US9070828B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9070828-B2 |
| Application number | US-201414476081-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 3, 2014 |
| Priority date | Sep 30, 2009 |
| Publication date | Jun 30, 2015 |
| Grant date | Jun 30, 2015 |
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Abstract
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In a semiconductor device 100 , it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 with a front surface 10 a having a specific plane orientation. Accordingly, a high-resistivity layer is prevented from being formed at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 . Consequently, it is possible to improve the emission intensity of the semiconductor device 100.
First claim
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The invention claimed is: 1. A group III nitride semiconductor substrate, comprising a surface layer on a surface of the group III nitride semiconductor substrate, wherein the surface layer has a surface concentration density of 120×10 10 pieces/cm 2 to 15000×10 10 pieces/cm 2 of chlorine and has a surface concentration density of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfur, a thickness of an affected layer is 20 nm or less, and an inclination angle of a n…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P14/2908Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9070828B2 cover?
- In a semiconductor device 100 , it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 with a front surface 10 a having a specific plane…
- Who is the assignee on this patent?
- Sumitomo Electric Industries
- What technology area does this patent fall under?
- Primary CPC classification H10P14/2908. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 30 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).