Display apparatus and method of manufacturing the same
US-2024419215-A1 · Dec 19, 2024 · US
Method for making a light emitting diode having three dimensional nano-structures
US9070823B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9070823-B2 |
| Application number | US-201213728043-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 27, 2012 |
| Priority date | Mar 30, 2012 |
| Publication date | Jun 30, 2015 |
| Grant date | Jun 30, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A method for making a LED comprises following steps. A substrate having a surface is provided. A first semiconductor layer, an active layer and a second semiconductor pre-layer is formed on the surface of the substrate. A patterned mask layer is applied on a surface of the second semiconductor pre-layer. A number of three-dimensional nano-structures is formed on the second semiconductor pre-layer and the patterned mask layer is removed. The substrate is removed and a first electrode is formed on a surface of the first semiconductor layer away from the active layer. A second electrode is formed to electrically connect with the second semiconductor pre-layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for making a light emitting diode, comprising steps of: providing a substrate having a first surface; forming a first semiconductor layer, an active layer and a second semiconductor pre-layer on the first surface; applying a patterned mask layer on a second semiconductor pre-layer surface, wherein the patterned mask layer comprises a plurality of linear walls aligned side by side, and a groove is defined between each adjacent linear walls to for…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9070823B2 cover?
- A method for making a LED comprises following steps. A substrate having a surface is provided. A first semiconductor layer, an active layer and a second semiconductor pre-layer is formed on the surface of the substrate. A patterned mask layer is applied on a surface of the second semiconductor pre-layer. A number of three-dimensional nano-structures is formed on the second semiconductor pre-lay…
- Who is the assignee on this patent?
- Univ Tsinghua, Hon Hai Prec Ind Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10H20/01. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 30 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).