Capacitor having conducitve pillar structures configured to increase capacitance density
US-2024304662-A1 · Sep 12, 2024 · US
US9070751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9070751-B2 |
| Application number | US-201313835429-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2013 |
| Priority date | Mar 12, 2013 |
| Publication date | Jun 30, 2015 |
| Grant date | Jun 30, 2015 |
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A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor device, comprising: establishing a signal conductor layer formed of an insulating material and channels, the signal conductor layer having: a first channel and a second channel, the first channel and the second channel having a substantially equivalent cross-sectional area, and the insulating material bordering at least three edges of the first channel and bordering at least three edges of the second channel;…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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