Method for fabricating a connection region in a semiconductor device

Patent metadata

Field	Value
Publication number	US-9070592-B2
Application number	US-201313888307-A
Country	US
Kind code	B2
Filing date	May 6, 2013
Priority date	Feb 27, 2009
Publication date	Jun 30, 2015
Grant date	Jun 30, 2015

Abstract

Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a buried-type wordline in an active region defined on a SOI substrate, forming a silicon connection region for connecting an upper silicon layer to a lower silicon layer between neighboring buried type wordlines, and recovering the upper silicon layer on the silicon connection region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first buried-type wordline in an active region defined in a silicon on insulator (SOI) substrate, the SOI substrate including a lower silicon layer, an upper silicon layer, and a buried insulating layer separating the lower silicon layer from the upper silicon layer;
a silicon connection region, located between the first buried-type wordline and a second buried-type wordline, the silicon connection region configured to…

Assignees

• Sk Hynix Inc

Inventors

• Lee Sang Soo

Classifications

• H10W20/021

  Electricity · mapped topic

• H10D12/038

  Electricity · mapped topic

• H10D86/201 Primary

  Electricity · mapped topic

• H01L27/1203 Primary

  Electricity · mapped topic

• H01L21/743

  Electricity · mapped topic