Capacitor from second level middle-of-line layer in combination with decoupling capacitors
US-9478490-B2 · Oct 25, 2016 · US
US9070575B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9070575-B2 |
| Application number | US-201313953476-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 29, 2013 |
| Priority date | Sep 8, 2011 |
| Publication date | Jun 30, 2015 |
| Grant date | Jun 30, 2015 |
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Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.
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What is claimed is: 1. An integrated circuit formed at a semiconducting surface of a substrate, comprising: a plurality of non-volatile memory cells, each memory cell comprising a memory cell capacitor having a capacitor dielectric formed of a ferroelectric material; first and second ferroelectric capacitors, each having a capacitor dielectric formed of the ferroelectric material, disposed between first and second plates, wherein the second plate of the first ferroelectric capac…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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