Stack packages having token ring loops

US9070570B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9070570-B2
Application numberUS-201414533668-A
CountryUS
Kind codeB2
Filing dateNov 5, 2014
Priority dateDec 20, 2012
Publication dateJun 30, 2015
Grant dateJun 30, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.

First claim

Opening claim text (preview).

What is claimed is: 1. A stack package comprising: a substrate having a first bond finger, a second bond finger and a third bond finger; a first semiconductor chip group including a plurality first semiconductor chips stacked on the substrate and a second semiconductor chip group including a plurality of second semiconductor chips stacked on the first semiconductor chip group, each of the first semiconductor chips and the second semiconductor chips having an input bonding pad, a…

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What does patent US9070570B2 cover?
Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of …
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 30 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).