Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Semiconductor memory devices and semiconductor packages
US9070569B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9070569-B2 |
| Application number | US-201414450359-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 4, 2014 |
| Priority date | Feb 9, 2010 |
| Publication date | Jun 30, 2015 |
| Grant date | Jun 30, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device comprising: a plurality of semiconductor dies that are stacked, each semiconductor die including a plurality of memory cell arrays; and a plurality of input-output bump pad parts respectively located at a central region of each semiconductor die, the input-output bump pad parts providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9070569B2 cover?
- A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The…
- Who is the assignee on this patent?
- Lee Ho-Cheol, Oh Chi-Sung, Kim Jin-Kuk, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 30 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).