Multiple programming of flash memory without erase

Patent metadata

Field	Value
Publication number	US-9070453-B2
Application number	US-201113086408-A
Country	US
Kind code	B2
Filing date	Apr 14, 2011
Priority date	Apr 15, 2010
Publication date	Jun 30, 2015
Grant date	Jun 30, 2015

Abstract

To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.

First claim

What is claimed is:

1. A method of attempting to store, successively, in a plurality of memory cells, a first plurality of input bits and a second plurality of input bits, comprising:
(a) providing a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level;
(b) transforming the first plurality of input bits to a first plurality of transformed bits, using a first transformation, wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels;
(c) programming at least a first portion of the memory cells to store the first plurality of transformed bits according to the mapping; and
(d) subsequent to the programming of the at least first portion of the memory cells, and without erasing at least a second portion of the memory cells that includes the at least first portion of the memory cells:
(i) determining, for the at least second portion of the memory cells, whether respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, a second plurality of transformed bits obtained by transforming the second plurality of input bits using a second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(ii) only if the respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, the second plurality of transformed bits obtained by transforming the second plurality of input bits using the second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells: programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping.

2. The method of claim 1 , wherein the second plurality of input bits is equal in number to the first plurality of input bits.

3. The method of claim 1 , wherein the first transformation is a variable-output-length transformation.

4. The method of claim 3 , wherein the first transformation includes a variable-length prefix encoding of the first plurality of input bits.

5. The method of claim 4 , wherein the variable-length prefix encoding is selected from the group consisting of a reverse Huffman encoding and a reverse arithmetic encoding.

6. The method of claim 4 , wherein each memory cell has more than two cell levels, and wherein the method further comprises:
(e) designing the variable-length prefix encoding to induce a predefined probability distribution over the cell levels.

7. The method of claim 6 , wherein the predefined probability distribution is optimized relative to a number of redundancy bits per constrained cell for the programming of the at least second portion of the memory cells.

8. The method of claim 6 , wherein a number of redundancy bits per constrained cell for the programming of the at least second portion of the memory cells is chosen in accordance with the predefined probability distribution.

9. The method of claim 6 , wherein each memory cell has at least eight cell levels and wherein the programming of the at least second portion of the memory cells requires an overhead of at most about 27%.

10. The method of claim 1 , wherein the first transformation is a fixed-output-length transformation.

11. The method of claim 10 , wherein the first transformation includes trellis encoding of the first plurality of input bits.

12. The method of claim 10 , wherein the first transformation includes reverse enumerative source encoding of the first plurality of input bits.

13. The method of claim 10 , wherein the first transformation includes an encoding based on a non-bijective mapping of the first plurality of input bits.

14. The method of claim 1 , further comprising: (e) prior to programming the at least first portion of the memory cells to store the first plurality of transformed bits according to the mapping: erasing the at least first portion of the memory cells.

15. The method of claim 1 , wherein the second transformation includes algebraic coset encoding of the second plurality of input bits.

16. The method of claim 1 , wherein the second transformation includes erasure coset encoding of the second plurality of input bits to produce an erasure coset codeword.

17. The method of claim 16 , wherein the erasure coset encoding includes a plurality of hard constraints on the second plurality of transformed bits.

18. The method of claim 16 , wherein the erasure coset encoding includes a plurality of soft constraints on the second plurality of transformed bits.

19. The method of claim 16 , wherein the erasure coset encoding is iterative.

20. The method of claim 16 , wherein the second transformation includes finding at least one error correction redundancy bit such that error correction decoding of a combination of the erasure coset codeword and the at least one error correction redundancy bit, followed by erasure coset decoding of the results of the error correction decoding, reproduces the second plurality of input bits.

21. The method of claim 1 , wherein, following the determining step, if the respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, the second plurality of transformed bits obtained by transforming the second plurality of input bits using the second transformation, are inaccessible from the current respective cell levels of the at least second portion of the memory cells: erasing the at least second portion of the memory cells and then programming the at least second portion of memory cells to store the second plurality of input bits according to the mapping.

22. A memory device comprising:
(a) a plurality of memory cells; and
(b) a controller operative to attempt to store, successively, in the plurality of memory cells, a first plurality of input bits and a second plurality of input bits, by:
(i) transforming the first plurality of input bits to a first plurality of transformed bits, using a first transformation,
(ii) programming at least a first portion of the memory cells to store the first plurality of transformed bits according to a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level and wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels, and
(iii) subsequent to the programming of the at least first portion of the memory cells, and without erasing at least a second portion of the memory cells that includes the at least first portion of the memory

Assignees

• Sharon Eran
• Alrod Idan
• Litsyn Simon
• Ilani Ishai
• Univ Ramot

Inventors

• Sharon Eran
• Alrod Idan
• Litsyn Simon
• Ilani Ishai

Classifications

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G06F12/02

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/102 Primary

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title