Methods of forming fine patterns in semiconductor devices

Patent metadata

Field	Value
Publication number	US-9070448-B2
Application number	US-201414334984-A
Country	US
Kind code	B2
Filing date	Jul 18, 2014
Priority date	Aug 11, 2008
Publication date	Jun 30, 2015
Grant date	Jun 30, 2015

Abstract

Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

First claim

What is claimed:

1. A memory device comprising:
a first contact pad in a contact region of the memory device;
a second contact pad in the contact region directly adjacent to the first contact pad, the first and second contact pads comprising a pair of contact pads for a memory block in the memory device;
a first conductive line comprising a first long portion extending in a first direction and a first short portion extending in a second direction that is different than the first direction, the first short portion extending from the first contact pad to the first long portion, and the first long portion extending to the memory block in a cell array region of the memory device;
a second conductive line, directly adjacent to the first conductive line, the second conductive line comprising a second long portion extending in the first direction and a second short portion extending in the second direction, the second short portion extending from the second contact pad to the second long portion, and the second long portion extending to the memory block; and
a dummy conductive pattern between the first and second short portions in the contact region.

2. The memory device of claim 1 wherein the dummy conductive pattern extends between the first and second short portions toward ends of the first and second contact pads, the first and second short portions ending short of the ends of the first and second contact pads.

3. The memory device of claim 2 wherein the dummy conductive pattern includes an opening to define a U shaped dummy conductive pattern wherein the opening faces towards the ends of the first and second contact pads.

4. The memory device of claim 2 wherein the end of the first contact pad and the end of the second contact pad are aligned to one another in the first direction so that one end does not extend beyond the other in the second direction.

5. The memory device of claim 3 wherein the dummy conductive pattern further comprises:
a first portion of the dummy conductive pattern extending alongside the first short portion of the first conductive line for a first length toward the first contact pad to an end point of the first portion that is short of the end of the first contact pad; and
a second portion of the dummy conductive pattern, spaced apart from the first portion of the dummy conductive pattern, the second portion extending alongside the second short portion of the second conductive line for the first length toward the second contact pad to an end point of the second portion that is short of the end of the second contact pad.

6. The memory device of claim 5 wherein the first and second contact pads are wider than both of the first and second portions of the dummy conductive patterns in the first direction.

7. The memory device of claim 6 wherein the first and second contact pads are wider than the first and second short portions, respectively, in the first direction.

8. The memory device of claim 1 wherein the first conductive line comprises a first L shaped conductive line and wherein the second conductive line comprises a second L shaped conductive line.

9. The memory device of claim 1 further comprising:
a ground select line including a first bar shaped portion extending in the first direction; and
a string select line including a second bar shaped portion extending in the first direction, wherein the first and second long portions extend between the first and second bar shaped portions.

10. A NAND Flash memory device comprising:
first and second directly adjacent contact pads defining a first pair of contact pads in a contact region of the NAND Flash memory device, the first pair of contact pads electrically coupled to a first memory cell block in the NAND Flash memory device;
third and fourth directly adjacent contact pads defining a second pair of contact pads in the contact region of the NAND Flash memory device, the second pair of contact pads electrically coupled to a second memory cell block that is directly adjacent to the first memory cell block;
a first U shaped dummy conductive line including a first opening that faces a space between the first pair of contact pads; and
a second U shaped dummy conductive line including a second opening that faces away from the first opening and towards a space between the second pair of contact pads.

11. The NAND Flash memory device of claim 10 , the device further comprising:
a first L shaped conductive line coupling the first contact pad to the first memory cell block;
a second L shaped conductive line coupling the second contact pad to the first memory cell block, the second L shaped conductive line following a profile of the first L shaped conductive line;
a third L shaped conductive line coupling the third contact pad to the second memory cell block; and
a fourth L shaped conductive line coupling the fourth contact pad to the second memory cell block, the fourth L shaped conductive line following a profile of the third L shaped conductive line.

12. The NAND Flash memory device of claim 11 , wherein the first and third L shaped conductive lines are mirror image L shapes of each other relative to an axis extending in a direction toward the first and second memory blocks alongside the first through fourth L shaped conductive lines.

13. The NAND Flash memory device of claim 11 further comprising:
a ground select line including a first bar shaped portion; and
a string select line including a second bar shaped portion, wherein the first-fourth L shaped conductive lines are located between the first and second bar shaped portions.

14. The NAND Flash memory device of claim 10 wherein the first U shaped dummy conductive line extends toward ends of the first and second contact pads and ends short of the ends of the first and second contact pads.

15. The NAND Flash memory device of claim 14 wherein the end of the first contact pad and the end of the second contact pad are aligned to one another.

16. The NAND Flash memory device of claim 11 wherein the first and second contact pads are wider than a portion of the first U shaped dummy conductive line that extends parallel to the first and second contact pads; and
wherein the third and fourth contact pads are wider than a portion of the second U shaped dummy conductive line that extends parallel to the third and fourth contact pads.

17. The NAND Flash memory device of claim 11 wherein the first and second contact pads each have a shape that is a mirror image of the other relative to an axis extending between the first and second contact pads; and
the third and fourth contact pads each have a shape that is a mirror image of the other relative to the axis extending between the third and fourth contact pads.

18. The NAND Flash memory device of claim 10 further comprising:
a plurality of first U shaped dummy conductive lines including the first U shaped dummy conductive line; and
a plurality of second U shaped dummy conductive lines including the second U shaped dummy conductive line, ones of the pluralities of the first and second U shaped dummy conductive lines are decreasingly spaced apart from one another as a distance to the first and second memory blocks increases.

19. A NAND Flash memory device comprising:
a first contact pad in a contact region of the NAND Flash memory device;
a second contact pad in the contact region directly adjacent to the first contact pad, the first and second contact pads comprising a pair of contact pads for a memory block in the NAND Flash memory device;
a first

Assignees

• Min Jae-Ho
• Kwon O-Lk
• Kim Bum-Soo
• Kim Dong-Chan
• Kim Myeong-Cheol
• Samsung Electronics Co Ltd

Inventors

• Min Jae-Ho
• Kwon O-Lk
• Kim Bum-Soo
• Kim Dong-Chan
• Kim Myeong-Cheol

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H01L21/32139

  Electricity · mapped topic