Uplink data congestion detection for low-latency services in wireless communication networks
US-2024373448-A1 · Nov 7, 2024 · US
Network interface and method of aggregating processor circuits
US9065747B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9065747-B2 |
| Application number | US-201213730483-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 28, 2012 |
| Priority date | Dec 28, 2012 |
| Publication date | Jun 23, 2015 |
| Grant date | Jun 23, 2015 |
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Abstract
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A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled with the second transponder and the cell engine so as to transmit a body cell to the cell engine. The system may aggregate the processing capacity of several processor circuits to form larger capacity logical interfaces. Packets may be fragmented into a header cell including the packet header and body cells including the packet payload and then transmit and reassemble the packet. The header cells may be fully handled by the processor circuit, while body cells may be passed on without processing.
First claim
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What is claimed is: 1. An egress interface, comprising: a cell engine configured to receive a packet having a packet header and a payload, segment the packet into a first cell including the packet header and a second cell including at least a portion of the payload of the packet, the first cell having a first header including routing information and the second cell having a second header, assign sequence numbers to the first cell and the second cell, such that the the first and se…
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- What does patent US9065747B2 cover?
- A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled w…
- Who is the assignee on this patent?
- Infinera Corp
- What technology area does this patent fall under?
- Primary CPC classification H04L47/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 23 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).