Multimode Decoder Implementation Method and Device
US-2015381211-A1 · Dec 31, 2015 · US
Method for performing channel interleaving in a multi-antenna wireless communication system, and apparatus for same
US9065622B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9065622-B2 |
| Application number | US-201414523568-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 24, 2014 |
| Priority date | May 12, 2010 |
| Publication date | Jun 23, 2015 |
| Grant date | Jun 23, 2015 |
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Abstract
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A method of transmitting a signal to a base station at a user equipment (UE) in a multi-antenna wireless communication system, can include generating interleaver input vector sequences, wherein the interleaver input vector sequences comprise vectors having a predetermined bit size, mapping the interleaver input vector sequences to an interleaver matrix, generating an output bit sequence by reading the interleaver matrix column by column, and transmitting the output bit sequence to the base station, wherein the predetermined bit size is defined by a product of a modulation order Q p m and the number N L of transmission layers.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of transmitting a signal to a base station at a user equipment (UE) in a multi-antenna wireless communication system, the method comprising: generating interleaver input vector sequences, wherein the interleaver input vector sequences comprise vectors having a predetermined bit size; mapping the interleaver input vector sequences to an interleaver matrix; generating an output bit sequence by reading the interleaver matrix column by column; and…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9065622B2 cover?
- A method of transmitting a signal to a base station at a user equipment (UE) in a multi-antenna wireless communication system, can include generating interleaver input vector sequences, wherein the interleaver input vector sequences comprise vectors having a predetermined bit size, mapping the interleaver input vector sequences to an interleaver matrix, generating an output bit sequence by read…
- Who is the assignee on this patent?
- Lg Electronics Inc
- What technology area does this patent fall under?
- Primary CPC classification H03M13/6525. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 23 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).