Method and apparatus for smoothing jitter generated by byte stuffing

Patent metadata

Field	Value
Publication number	US-9065610-B2
Application number	US-201313865843-A
Country	US
Kind code	B2
Filing date	Apr 18, 2013
Priority date	Apr 18, 2013
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte.

First claim

What is claimed is:

1. A method of jitter attenuation, said method comprising:
providing an input signal to a phase lock loop (PLL);
detecting a phase difference between said input signal and a feedback signal of said PLL and generating a first phase error signal; and
converting said first phase error signal to a second phase error signal comprising a smaller average gradient than said first phase error signal, wherein:
said converting said first phase error signal comprises…

Assignees

• Applied Micro Circuits Corp

Inventors

• Azenkot Yehuda
• Walker Timothy P

Classifications

• H04J3/076

  Electricity · mapped topic

• H03L7/081

  Electricity · mapped topic

• H04L1/004 Primary

  Electricity · mapped topic

• H03L7/1077 Primary

  Electricity · mapped topic

• H03L2207/50

  Electricity · mapped topic