Controlling nonvolatile memory device and nonvolatile memory system
US-9195541-B2 · Nov 24, 2015 · US
Bad wordline/array detection in memory
US9065481B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9065481-B2 |
| Application number | US-201313747842-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 23, 2013 |
| Priority date | Jun 15, 2012 |
| Publication date | Jun 23, 2015 |
| Grant date | Jun 23, 2015 |
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Abstract
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A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for a cache coupled to a computer system, the method comprising: reading multiple error correcting code (ECC) words of an individual wordline from the cache, the wordline comprising two or more ECC words which are read; detecting, by a controller of the computer system, a first error in a first ECC word and a second error in a second ECC word in the wordline that is read; identifying, by the controller of the computer system, the wordline as a f…
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Classifications
- H03M13/05Primary
Electricity · mapped topic
Physics · mapped topic
- G06F11/1064Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9065481B2 cover?
- A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline.…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H03M13/05. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 23 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).