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Integrated power-on-reset circuit
US9065451B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9065451-B2 |
| Application number | US-201314106470-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 13, 2013 |
| Priority date | Dec 21, 2012 |
| Publication date | Jun 23, 2015 |
| Grant date | Jun 23, 2015 |
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Abstract
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An integrated power-on reset circuit comprises a resistor and a capacitor, wherein the resistor is arranged to pass a current by quantum tunneling in order to charge the capacitor.
First claim
Opening claim text (preview).
The invention claimed is: 1. An integrated power-on reset circuit comprising a resistor and a capacitor, wherein the resistor is a field-effect transistor with a gate dielectric layer thickness of around 5 nanometers or less and is arranged to pass a current to the capacitor by quantum tunneling of charge through said gate dielectric layer in order to charge the capacitor, and wherein the circuit is an integrated power-on reset circuit and is arranged to output a reset signal when…
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- H03K17/223Primary
Electricity · mapped topic
- H03L5/00Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9065451B2 cover?
- An integrated power-on reset circuit comprises a resistor and a capacitor, wherein the resistor is arranged to pass a current by quantum tunneling in order to charge the capacitor.
- Who is the assignee on this patent?
- Nordic Semiconductor Asa
- What technology area does this patent fall under?
- Primary CPC classification H03K17/223. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 23 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).