Method for removing oxide film formed on surface of silicon wafer

US9064809B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9064809-B2
Application numberUS-201313760416-A
CountryUS
Kind codeB2
Filing dateFeb 6, 2013
Priority dateFeb 29, 2012
Publication dateJun 23, 2015
Grant dateJun 23, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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Disclosed is a method for removing an oxide film formed on a surface of a silicon wafer, comprising steps of: preparing a silicon wafer having an oxide film formed thereon; arranging a discoid wafer mounting stage, which has a contact portion with the oxide film being formed of an acid-resistant resin layer, in a reaction container of a vapor-phase etching apparatus; mounting the silicon wafer on the mounting stage in such a manner that a wafer center coincides with a central axis of the mounting stage; and circulating a hydrogen fluoride containing gas into the reaction container and removing the oxide film from an interface between a chamfered surface and a wafer lower surface toward the inner side of the wafer until a desired interval a is obtained, wherein the desired interval a is adjusted by changing a stage diameter of the mounting stage.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for removing an oxide film formed on a surface of a silicon wafer, comprising: preparing a silicon wafer which has an upper surface, a lower surface, a chamfered surface, and an end surface and has an oxide film formed on at least the entire lower surface of the silicon wafer; arranging one or more discoid wafer mounting stages, each of which has at least a contact portion with the oxide film being formed of an acid-resistant resin layer, in a rea…

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What does patent US9064809B2 cover?
Disclosed is a method for removing an oxide film formed on a surface of a silicon wafer, comprising steps of: preparing a silicon wafer having an oxide film formed thereon; arranging a discoid wafer mounting stage, which has a contact portion with the oxide film being formed of an acid-resistant resin layer, in a reaction container of a vapor-phase etching apparatus; mounting the silicon wafer …
Who is the assignee on this patent?
Sumco Corp
What technology area does this patent fall under?
Primary CPC classification H10P50/283. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 23 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).