Devices and methods related to field-effect transistor structures for radio-frequency applications

Patent metadata

Field	Value
Publication number	US-9064746-B2
Application number	US-201213672410-A
Country	US
Kind code	B2
Filing date	Nov 8, 2012
Priority date	Nov 9, 2011
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

Disclosed are devices and methods related to field-effect transistor (FET) structures configured to provide reduced per-area values of resistance in the linear operating region (Rds-on). Typical FET devices such as silicon-on-insulator (SOI) device require larger device sizes to desirably lower the Rds-on values. However, such increases in size result in undesirably larger die sizes. Disclosed are various examples of shapes of source, drain, and corresponding gate that yield reduced Rds-on values without having to increase the device size. In some implementations, such FET devices can be utilized in high power radio-frequency (RF) switching applications.

First claim

What is claimed is:

1. A transistor, comprising:
a semiconductor substrate;
a plurality of first diffusion regions formed on the semiconductor substrate;
a plurality of second diffusion regions formed on the semiconductor substrate; and
a gate layer disposed over the first and second diffusion regions, the gate layer defining a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions, at least some of the first and second openings having a shape other than a rectangle, neighboring pairs of the first and second openings being arranged such that the first opening in a respective neighboring pair is approximately perpendicular to the second opening in the respective neighboring pair, a neighboring pair of first and second openings including a first facing portion for the first opening and a second facing portion for the second opening, the first facing portion and the second facing portion defining a “v” shaped facing area therebetween.

2. The transistor of claim 1 further comprising a contact feature formed on each of the first and second diffusion regions.

3. The transistor of claim 2 further comprising a first conductor that electrically connects the contact features on the first diffusion regions, and a second conductor that electrically connects the contact features on the second diffusion regions.

4. The transistor of claim 3 wherein the first conductor is further connected to a source terminal and the second conductor is further connected to a drain terminal.

5. The transistor of claim 4 wherein at least some of the first openings have an elongation axis along a first direction.

6. The transistor of claim 5 wherein at least some of the second openings have an elongation axis along a second direction that is approximately perpendicular to the first direction.

7. The transistor of claim 1 wherein each of the first conductor and the second conductor extends in a zigzag along a first direction.

8. The transistor of claim 7 wherein the first openings are arranged at corners of the zigzag of the first conductor and the second openings are arranged at corners of the zigzag of the second conductor.

9. The transistor of claim 1 wherein the transistor is a metal-oxide-semiconductor FET (MOSFET).

10. The transistor of claim 1 further comprising an insulator layer disposed below the semiconductor substrate that includes a silicon substrate to yield a silicon-on-insulator (SOI) structure.

11. The transistor of claim 1 wherein the shape is dimensioned to yield a reduced value of Rds-on per area when compared to a transistor having a similar sized rectangular opening.

12. The transistor of claim 1 wherein each of the first and second openings have a shape defined by two rhombuses with their corners overlapping.

13. A semiconductor die, comprising:
a semiconductor substrate; and
a plurality of transistors implemented on the substrate, each transistor including a plurality of first diffusion regions and a plurality of second diffusion regions, each transistor further including a gate layer disposed over the first and second diffusion regions, the gate layer defining a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions, at least some of the first and second openings having a shape other than a rectangle, neighboring pairs of the first and second openings being arranged such that the first opening in a respective neighboring pair is approximately perpendicular to the second opening in the respective neighboring pair, a neighboring pair of first and second openings including a first facing portion for the first opening and a second facing portion for the second opening, the first facing portion and the second facing portion defining a “v” shaped facing area therebetween.

14. The semiconductor die of claim 13 wherein each of the first and second openings have a shape defined by two rhombuses with their corners overlapping.

15. The semiconductor die of claim 13 further comprising a contact feature formed on each of the first and second diffusion regions, a first conductor that electrically connects the contact features on the first diffusion regions, and a second conductor that electrically connects the contact features on the second diffusion regions, each of the first conductor and the second conductor extending in a zigzag along a first direction.

16. A radio-frequency (RF) device, comprising:
a transceiver configured to process RF signals;
a power amplifier configured to amplify an RF signal generated by the transceiver;
an antenna in communication with the transceiver and configured to facilitate transmission of the amplified RF signal; and
a switching module coupled to the power amplifier and the antenna, the switching module configured to route the amplified RF signal from the power amplifier to the antenna, the switching module having a switch circuit including a plurality of transistors connected in series, each transistor including a plurality of first diffusion regions and a plurality of second diffusion regions, each transistor further including a gate layer disposed over the first and second diffusion regions, the gate layer defining a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions, at least some of the first and second openings having a shape other than a rectangle, neighboring pairs of the first and second openings being arranged such that the first opening in a respective neighboring pair is approximately perpendicular to the second opening in the respective neighboring pair, a neighboring pair of first and second openings including a first facing portion for the first opening and a second facing portion for the second opening, the first facing portion and the second facing portion defining a “v” shaped facing area therebetween.

17. The RF device of claim 16 wherein the RF device is a portable wireless device.

18. The RF device of claim 16 wherein each of the first and second openings have a shape defined by two rhombuses with their corners overlapping.

19. The RF device of claim 16 further comprising a contact feature formed on each of the first and second diffusion regions, a first conductor that electrically connects the contact features on the first diffusion regions, and a second conductor that electrically connects the contact features on the second diffusion regions, each of the first conductor and the second conductor extending in a zigzag along a first direction.

Assignees

• Skyworks Solutions Inc

Inventors

• Crandall Jonathan Christian

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H04B1/38

  Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving · CPC title