Lock and key through-via method for wafer level 3D integration and structures produced thereby

Patent metadata

Field	Value
Publication number	US-9064717-B2
Application number	US-61517509-A
Country	US
Kind code	B2
Filing date	Nov 9, 2009
Priority date	Sep 26, 2008
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

First claim

We claim:

1. A structure comprising two device layers joined together to form an electronic system and further comprising:
a first device layer disposed on a first substrate and comprising a first circuit layer and a first interconnection wiring layer;
a second device layer disposed on a second substrate and comprising a second circuit layer and a second interconnection wiring layer;
said first and said second device layers further connected using two sets of via connections comprising a first via connection that extends from about the top surface of said first interconnection wiring layer of said first device layer to about the top surface of said second interconnection wiring layer of said second device layer; and a second via connection that extends from about said top surface of said first interconnection wiring layer of said first device layer through said second device layer, and connecting to a third set of connections comprising interconnection wires and input output terminals disposed on the back side of said second device layer.

2. A structure according to claim 1 further comprising an adhesive layer disposed between said top surface of said first device layer and said top surface of said second device layer and surrounding a portion of the height of said first via connection and said second via connection.

3. A structure according to claim 2 further comprising an optional passivation coating to protect the sidewalls of said first via connection and said second via connection in said portions where they are surrounded by said adhesive layer.

4. A structure according to claim 1 further comprising at least one more device layer in the manner of said second device layer, stacked on and attached to the back side of said second device layer and connected to said first and said second device layers and said third set of connections by means of additional via connections.

5. A structure according to claim 1 wherein said circuits in said first and second device layer comprise any one of logic circuits, memory circuits, controller circuits, image processing circuits, optoelectronic circuits and combinations thereof.

6. A structure according to claim 1 wherein said interconnect layers in said second device layer comprise dual damascene wiring and vias, through substrate vias and combinations thereof.

7. A structure according to claim 1 wherein said first and second substrates comprise silicon, or gallium arsenide, or silicon carbide.

8. A structure according to claim 2 wherein said adhesive layer comprises a polyimide adhesive, or benzocyclobutene adhesive, or polyarylene ether adhesive, or epoxy adhesive.

9. A structure according to claim 1 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

10. A structure according to claim 2 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

11. A structure according to claim 3 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

12. A structure according to claim 4 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

13. A structure according to claim 5 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

14. A structure according to claim 6 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

15. A structure according to claim 7 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

16. A structure according to claim 8 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.

Assignees

• Purushothaman Sampath
• Rothwell Mary E
• Shahidi Ghavam Ghavami
• Yu Roy Rongqing
• IBM

Inventors

• Purushothaman Sampath
• Rothwell Mary E
• Shahidi Ghavam Ghavami
• Yu Roy Rongqing

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/07227

  involving guiding structures, e.g. spacers or supporting members · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/072

  of bump connectors · CPC title