Methods and apparatus for soft data generation for memory devices based on performance factor adjustment

Patent metadata

Field	Value
Publication number	US-9064594-B2
Application number	US-200913063874-A
Country	US
Kind code	B2
Filing date	Sep 30, 2009
Priority date	Sep 30, 2008
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

Methods and apparatus are provided for soft data generation for memory devices based on a performance factor adjustment. At least one soft data value is generated for a memory device, such as a flash memory device, by obtaining at least one read value; and generating the soft data value based on the obtained at least one read value and an adjustment based on one or more performance factors of the memory device. The read values may be soft data or hard data. Possible performance factors include endurance, number of read cycles, retention time, temperature, process corner, inter-cell interference impact, location and a pattern of aggressor cells. One or more pattern-dependent and/or location-specific performance factors may also be considered. The generated soft data value may be a soft read value used to generate one or more log likelihood ratios or may be the log likelihood ratios themselves.

First claim

We claim:

1. A method for generating at least one soft data value for a memory device, comprising the steps of:
obtaining at least one read value from said memory device;
obtaining at least one nominal value based on said at least one read value obtained from said memory device, wherein said at least one nominal value indicates a reliability of at least one bit of said at least one read value;
obtaining at least one offset value based on one or more performance factors of said memory device; and
generating said at least one soft data value by applying said at least one offset value to said at least one nominal value.

2. The method of claim 1 , wherein said one or more performance factors comprise one or more of endurance, number of program/erase cycles, number of read cycles, retention time, temperature, temperature changes, process corner, inter-cell interference impact, location of a memory cell within the memory device, location of a wordline from which said at least one read value is obtained, location of a page from which said at least one read value is obtained, location of a page within a wordline from which said at least one read value is obtained, and a pattern of aggressor cells.

3. The method of claim 1 , wherein said at least one offset is based on separate performance factors for one or more of different bits within a cell, different pages within a wordline, different bit lines, and different hard read data values.

4. The method of claim 1 , wherein said at least one read value comprises one or more of data bits, voltage levels, current levels and resistance levels.

5. The method of claim 1 , wherein said at least one read value comprises one or more of soft data and hard data.

6. The method of claim 1 , wherein said at least one soft data value comprises one or more of (i) a soft read value that is used to generate one or more log likelihood ratios, and (ii) one or more log likelihood ratios.

7. The method of claim 1 , wherein said at least one soft data value indicates a reliability of said at least one read value.

8. The method of claim 1 , wherein one or more of said steps are implemented by one or more of a controller, a read channel, a signal processing unit and a decoder.

9. The method of claim 1 , wherein said offset is obtained in advance and stored in said memory device.

10. The method of claim 1 , further comprising the step of measuring said offset.

11. The method of claim 1 , wherein said one or more performance factors comprise one or more pattern-dependent performance factors.

12. The method of claim 1 , wherein said one or more performance factors comprise one or more location-specific performance factors.

13. The method of claim 1 , wherein said memory device is a flash memory device.

14. The method of claim 1 , wherein said offset reduces a reliability value of said at least one read value.

15. The method of claim 1 , wherein said at least one offset reduces a reliability value of said nominal value by an amount equal to said offset value.

16. A system for generating at least one soft data value for a memory device, comprising:
a program memory; and
at least one processor, coupled to the program memory, operative to:
obtain at least one read value from said memory device;
obtain at least one nominal value based on said at least one read value obtained from said memory device, wherein said at least one nominal value indicates a reliability of at least one bit of said at least one read value;
obtain at least one offset value based on one or more performance factors of said memory device; and
generate said at least one soft data value by applying said at least one offset value to said at least one nominal value.

17. The system of claim 16 , wherein said one or more performance factors comprise one or more of endurance, number of program/erase cycles, number of read cycles, retention time, temperature, temperature changes, process corner, inter-cell interference impact, location of a memory cell within the memory device, location of a wordline from which said at least one read value is obtained, location of a page from which said at least one read value is obtained, location of a page within a word line from which said at least one read value is obtained, and a pattern of aggressor cells.

18. The system of claim 16 , wherein said at least one soft data value comprises one or more of (i) a soft read value that is used to generate one or more log likelihood ratios and (ii) one or more log likelihood ratios.

19. The system of claim 16 , wherein said memory device is a flash memory device.

20. The system of claim 16 , wherein said one or more performance factors comprise one or more location-specific performance factors.

Assignees

• Haratsch Erich F
• Yen Johnson
• Seagate Technology Llc

Inventors

• Haratsch Erich F
• Yen Johnson

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G11C2211/5634

  Reference cells · CPC title