Vertical capacitors with spaced conductive lines
US-2015357120-A1 · Dec 10, 2015 · US
Semiconductor devices and methods of fabricating the same
US9059331B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9059331-B2 |
| Application number | US-201414193071-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 28, 2014 |
| Priority date | Mar 5, 2013 |
| Publication date | Jun 16, 2015 |
| Grant date | Jun 16, 2015 |
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Abstract
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Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a semiconductor device, comprising: forming a molding layer on a semiconductor substrate; forming a first electrode that passes through the molding layer; exposing a part of the first electrode by partially etching the molding layer; forming a sacrificial oxide layer by oxidizing an exposed part of the first electrode; removing the partially-etched molding layer and the sacrificial oxide layer; forming a dielectric layer on…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D1/043Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9059331B2 cover?
- Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The par…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D1/043. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 16 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).