Array substrate and its manufacturing method

Patent metadata

Field	Value
Publication number	US-9059293-B2
Application number	US-201313967536-A
Country	US
Kind code	B2
Filing date	Aug 15, 2013
Priority date	Aug 17, 2012
Publication date	Jun 16, 2015
Grant date	Jun 16, 2015

Abstract

An array substrate comprises a substrate, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode being provided in different areas on the substrate and the vertical projections of the source electrode and the drain electrode on the substrate having an overlapping area; a semiconductor layer formed between the source electrode and the drain electrode, a vertical projection of the semiconductor layer on the substrate having overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate; a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode; a pixel electrode, a gate line, and a data line. A manufacturing method for the array substrate is also disclosed.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate, a gate electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are provided in different areas on the substrate, and vertical projections of the source electrode and the drain electrode on the substrate have an overlapping area;
a semiconductor layer formed between the source electrode and the drain electrode, wherein a vertical projection of the semiconductor layer on the substrate has overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate;
a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode;
a pixel electrodes electrically connected with the drain electrode;
a gate line electrically connected with the gate electrode;
a data line electrically connected with the source electrode; and
at least one groove formed on the substrate corresponding to one of the source electrode and the drain electrode.

2. The array substrate according to claim 1 , wherein the substrate is a glass substrate, or the substrate is a glass substrate formed with a passivation layer on its surface, and the passivation layer is formed on a side of the glass substrate to be formed with the source electrode or the drain electrode.

3. The array substrate according to claim 1 , wherein the at least one groove is formed on the substrate corresponding to the source electrode,
wherein the source electrode is formed in the groove of the substrate, the semiconductor layer is formed on the source electrode, the drain electrode is formed on the semiconductor layer, the first insulating layer is formed on the drain electrode, the pixel electrode is formed on the first insulating layer; wherein the pixel electrode is electrically connected with the drain electrode through the via hole on the first insulating layer.

4. The array substrate according to claim 1 , wherein the at least one groove is formed on the substrate corresponding to the source electrode and the data line respectively,
wherein the groove corresponding to the source electrode is communicated with the groove corresponding to the data line;
wherein the source electrode and the data line are formed in the corresponding grooves of the substrate respectively, the semiconductor layer is formed on the source electrode, the drain electrode is formed on the semiconductor layer, the first insulating layer is formed on the drain electrode, the pixel electrode is formed on the first insulating layer; and
wherein the pixel electrode is electrically connected with the drain electrode through the via hole on the first insulating layer.

5. The array substrate according to claim 1 , wherein the at least one groove is formed on the substrate corresponding to the drain electrode;
wherein the pixel electrode is formed on the substrate and a part of the pixel electrode is formed in the groove, the drain electrode is formed in the groove formed with the pixel electrode therein, the semiconductor layer is formed on the drain electrode, the source electrode is formed on the semiconductor layer, and the first insulating layer is formed on the source electrode.

6. The array substrate according to claim 1 , further comprising a first ohmic contact layer and a second ohmic contact layer,
wherein the first ohmic contact layer is formed between the source electrode and the semiconductor layer, the second ohmic contact layer is formed between the drain electrode and the semiconductor layer, and vertical projections of the first ohmic contact layer and the second ohmic contact layer have overlapping areas with the vertical projections of the source electrode, the drain electrode and the semiconductor layer on the substrate.

7. The array substrate according to claim 6 , wherein the vertical projections of the source electrode, the drain electrode, the semiconductor layer as well as the first ohmic contact layer and the second ohmic contact layer on the substrate overlap each other entirely.

8. The array substrate according to claim 1 , wherein the source electrode and the drain electrode are equal to each other in thickness.

9. The array substrate according to claim 1 , wherein the first insulating layer further comprises a portion formed on the substrate and below the gate electrode.

10. The array substrate according to claim 1 , wherein a vertical distance between the gate electrode and the source electrode equals to a vertical distance between the gate electrode and the drain electrode, and the overlapping area of the gate electrode with the source electrode equals to the overlapping area of the gate electrode with the drain electrode.

11. The array substrate according to claim 1 , further comprising a second insulating layer formed on the gate electrode.

12. An array substrate, comprising:
a substrate, a gate electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are provided in different areas on the substrate, and vertical projections of the source electrode and the drain electrode on the substrate have an overlapping area;
a semiconductor layer formed between the source electrode and the drain electrode, wherein a vertical projection of the semiconductor layer on the substrate has overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate;
a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode;
a pixel electrodes electrically connected with the drain electrode;
a gate line electrically connected with the gate electrode; and
a data line electrically connected with the source electrode;
wherein the pixel electrode, the drain electrode, the semiconductor layer, the source electrode and the first insulating layer are formed on the substrate in order, and the pixel electrode is formed on the substrate, the drain electrode is formed on the pixel electrode, the semiconductor layer is formed on the drain electrode, the source electrode is formed on the semiconductor layer, and the first insulating layer is formed on the source electrode.

13. The array substrate according to claim 12 , further comprising a first ohmic contact layer and a second ohmic contact layer,
wherein the first ohmic contact layer is formed between the source electrode and the semiconductor layer, the second ohmic contact layer is formed between the drain electrode and the semiconductor layer, and vertical projections of the first ohmic contact layer and the second ohmic contact layer have overlapping areas with the vertical projections of the source electrode, the drain electrode and the semiconductor layer on the substrate.

14. The array substrate according to claim 13 , wherein the vertical projections of the source electrode, the drain electrode, the semiconductor layer as well as the first ohmic contact layer and the second ohmic contact layer on the substrate overlap each other entirely.

15. The array substrate according to claim 12 , wherein the source electrode and the drain electrode are equal to each other in thickness.

16. The array substrate according to claim 12 , wherein a vertical distance between the gate electrode and the source electrode equals to a vertical distance between the gate electrode and the drain electrode, and the overlapping area of the gate electrode with the source electrode equals to the overlapping area of the gate electrode with the drain elect

Assignees

• Boe Technology Group Co Ltd

Inventors

• Gao Tao
• Lv Zhijun
• Li Tailiang

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D30/6746

  Amorphous silicon · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D30/6728 Primary

  Vertical TFTs · CPC title