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Tunneling field effect transistor and method for fabricating the same
US9059268B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9059268-B2 |
| Application number | US-201213641116-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 21, 2012 |
| Priority date | Feb 15, 2012 |
| Publication date | Jun 16, 2015 |
| Grant date | Jun 16, 2015 |
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Abstract
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A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate; a channel region formed in the semiconductor substrate, with one or more isolation structures formed in the channel region; a first buried layer and a second buried layer formed in the semiconductor substrate and located at both sides of the channel region respectively, the first buried layer being first type non-heavily-doped, and the second buried layer being second type non-heavily-doped; a source region and a drain region formed in the semiconductor substrate and located on the first buried layer and the second buried layer respectively; and a gate dielectric layer formed on the one or more isolation structures, and a gate formed on the gate dielectric layer.
First claim
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What is claimed is: 1. A tunneling field effect transistor, comprising: a semiconductor substrate; a channel region formed in the semiconductor substrate, with one or more isolation structures formed in the channel region; a first buried layer and a second buried layer formed in the semiconductor substrate and located at both sides of the channel region respectively, wherein the first buried layer is first type non-heavily-doped, and the second buried layer is second type non-…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9059268B2 cover?
- A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate; a channel region formed in the semiconductor substrate, with one or more isolation structures formed in the channel region; a first buried layer and a second buried layer formed in the semiconductor substrate and located at both side…
- Who is the assignee on this patent?
- Cui Ning, Liang Renrong, Wang Jing, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D62/151. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 16 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).