Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Methods of forming memory cells; and methods of forming vertical structures
US9059115B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9059115-B2 |
| Application number | US-201314097003-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 4, 2013 |
| Priority date | Jul 2, 2009 |
| Publication date | Jun 16, 2015 |
| Grant date | Jun 16, 2015 |
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Abstract
Official abstract text for this publication.
Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
First claim
Opening claim text (preview).
We claim: 1. A method of forming substantially vertical electrically conductive structures, comprising: photolithographically forming a series of laterally spaced-apart photoresist features over a substrate, each of the features having a substantially uniform lateral width, and simultaneously photolithographically forming another photoresist feature adjacent an end of said series; the other photoresist feature being spaced from the end of said series by a gap, and having a lateral…
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Inventors
Classifications
- H10P76/4085Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P50/264Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9059115B2 cover?
- Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into …
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P76/4085. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 16 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).