Semiconductor device

Patent metadata

Field	Value
Publication number	US-9059009-B2
Application number	US-201214368432-A
Country	US
Kind code	B2
Filing date	Dec 25, 2012
Priority date	Feb 9, 2012
Publication date	Jun 16, 2015
Grant date	Jun 16, 2015

Abstract

Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an insulating substrate with conductive patterns, having at least a first conductive pattern, a second conductive pattern, and a third conductive pattern, on a first insulating substrate;
a positive-electrode external lead terminal fixed to the first conductive pattern;
a negative-electrode external lead terminal fixed to the second conductive pattern;
an external lead terminal of intermediate potential fixed to the third conductive pattern;
a first semiconductor element having one surface fixed to the first conductive pattern;
a second semiconductor element having one surface fixed to the third conductive pattern; and
an insulating substrate with conductive pins, having conductive layers on front and rear surfaces of a second insulating substrate respectively, a plurality of first conductive pins fixed to the conductive layer on the rear surface of the second insulating substrate, and a plurality of second conductive pins fixed to the conductive layer on the front surface of the second insulating substrate,
wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are disposed adjacent to each other in parallel,
a portion of the pins constituting the plurality of first conductive pins is fixed to the other surface of the first semiconductor element, and another portion of pins constituting the plurality of first conductive pins are fixed to the third conductive pattern,
a portion of the pins constituting the plurality of second conductive pins is fixed to the other surface of the second semiconductor element, and another portion of the pins constituting the plurality of second conductive pins are fixed to the second conductive pattern,
the insulating substrate with conductive pins is disposed on the other surface of the first semiconductor element and the other surface of the second semiconductor element, and
an area in which the first semiconductor element and the second semiconductor element are disposed has a size substantially equivalent to a face of the insulating substrate with conductive pins.

2. A semiconductor device, comprising:
a first insulating substrate with conductive patterns having at least a first conductive pattern and a second conductive pattern, on a first insulating substrate;
a second insulating substrate with conductive patterns having at least a third conductive pattern on a third insulating substrate;
a positive-electrode external lead terminal fixed to the first conductive pattern;
a negative-electrode external lead terminal fixed to the second conductive pattern;
an external lead terminal of intermediate potential fixed to the third conductive pattern;
a first semiconductor element having one surface fixed to the first conductive pattern;
a second semiconductor element having one surface fixed to the third conductive pattern; and
an insulating substrate with conductive pins, having conductive layers on front and rear surfaces of a second insulating substrate respectively, a plurality of first conductive pins fixed to the conductive layer on the rear surface of the second insulating substrate, and a plurality of second conductive pins fixed to the conductive layer on the front surface of the second insulating substrate,
wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are disposed adjacent to each other in parallel,
a portion of pins constituting the plurality of first conductive pins is fixed to the other surface of the first semiconductor element, and another portion of pins constituting the plurality of first conductive pins are fixed to the third conductive pattern,
a portion of pins constituting the plurality of second conductive pins is fixed to another portion of surface of the second semiconductor element, and the other pins constituting the plurality of second conductive pins are fixed to the second conductive pattern, and
the insulating substrate with conductive pins is sandwiched between the other surface of the first semiconductor element and the other surface of the second semiconductor element.

3. The semiconductor device according to claim 1 , wherein the insulating substrate with conductive pins is a printed circuit board with metal pins comprising:
metal foil pieces fixed respectively to the front and rear surfaces of the second insulating substrate made of ceramic,
a first metal pin fixed to the metal foil piece on the rear surface, and
a second metal pin fixed to the metal foil piece on the front surface.

4. The semiconductor device according to claim 1 , wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are rectangular conductive plates.

5. The semiconductor device according to claim 1 , wherein the first semiconductor element and the second semiconductor element are connected in series through the first conductive pins and the third conductive pattern and are 2-in-1, 4-in-1, or 6-in-1 semiconductor modules each configuring an upper arm or a lower arm.

6. The semiconductor device according to claim 1 , wherein the first semiconductor element and the second semiconductor element each includes a switching transistor chip and a diode chip connected antiparallel to the switching transistor chip.

7. The semiconductor device according to claim 6 , wherein the switching transistor chip is an IGBT chip, a MOSFET chip, a junction field-effect transistor chip, or a bipolar transistor chip, and the diode chip is a pn diode chip or a Schottky barrier diode chip.

8. The semiconductor device according to claim 1 , wherein three sides of the second conductive pattern are surrounded by the first conductive pattern.

9. The semiconductor device according to claim 1 , wherein the plurality of second conductive pins fixed to the second conductive pattern penetrate the second insulating substrate.

10. The semiconductor device according to claim 2 , wherein the insulating substrate with conductive pins is a printed circuit board with metal pins comprising:
metal foil pieces fixed respectively to the front and rear surfaces of the second insulating substrate made of ceramic,
a first metal pin fixed to the metal foil piece on the rear surface, and
a second metal pin fixed to the metal foil piece on the front surface.

11. The semiconductor device according to claim 2 , wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are rectangular conductive plates.

12. The semiconductor device according to claim 2 , wherein the first semiconductor element and the second semiconductor element are connected in series through the first conductive pins and the third conductive pattern and are 2-in-1, 4-in-1, or 6-in-1 semiconductor modules each configuring an upper arm or a lower arm.

13. The semiconductor device according to claim 2 , wherein the first semiconductor element and the second semiconductor element each includes a switching transistor chip and a diode chip connected antiparallel to the switching transistor chip.

14. The semiconductor device according to claim 13 , wherein the switching transistor chip is an IGBT chip, a MOSFET chip, a junction field-effect transistor chip, or a bipolar transistor chip, and the diode chip is a pn diode chip or a Schottky barrier diode chip.

15. The semiconductor device according to claim 2 , wherein three sides of the second conductive pattern are surrounded by the first conductive pattern.

16. The semiconductor device according to claim 2 , wherein

Assignees

• Fuji Electric Co Ltd

Inventors

• Horio Masafumi
• Fukuda Kyohei
• Hori Motohito
• Ikeda Yoshinari

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title