Integrated circuits and methods to control access to multiple layers of memory

Patent metadata

Field	Value
Publication number	US-9058300-B2
Application number	US-6910508-A
Country	US
Kind code	B2
Filing date	Feb 7, 2008
Priority date	Mar 30, 2005
Publication date	Jun 16, 2015
Grant date	Jun 16, 2015

Abstract

Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

First claim

What is claimed is:

1. A memory access control circuit, comprising:
a silicon semiconductor substrate including a logic layer, the logic layer including circuitry fabricated on the silicon semiconductor substrate;
a third dimension memory in direct contact with and fabricated directly above the silicon semiconductor substrate and electrically coupled with at least a portion of the circuitry;
a memory access circuit included in the circuitry, the memory access circuit including…

Assignees

• Norman Robert
• Unity Semiconductor Corp

Inventors

• Norman Robert

Classifications

• G06F2212/2022

  Physics · mapped topic

• G11C16/08

  Physics · mapped topic

• G06F12/1483 Primary

  Physics · mapped topic

• G11C5/02

  Physics · mapped topic

• G06F12/1433

  Physics · mapped topic