Stackable multi-chip package system
US-9202776-B2 · Dec 1, 2015 · US
Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures
US9054091B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9054091-B2 |
| Application number | US-201313913770-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 10, 2013 |
| Priority date | Jun 10, 2013 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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Abstract
Official abstract text for this publication.
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
First claim
Opening claim text (preview).
The invention claimed is: 1. A hybrid packaging multi-chip semiconductor device comprising a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the lead frame unit comprises: a first die paddle and a second die paddle arranged side by side each having opposite first and second transverse edges and opposite first and second longitudinal edges, the second longitudinal edge of the…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9054091B2 cover?
- A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interco…
- Who is the assignee on this patent?
- Yilmaz Hamza, Xue Yan Xun, Lu Jun, and 5 more
- What technology area does this patent fall under?
- Primary CPC classification H10W70/442. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).