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Gate driving circuit and display panel having the same
US9053677B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9053677-B2 |
| Application number | US-201113313737-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 7, 2011 |
| Priority date | Jul 5, 2011 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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- Title
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Abstract
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Provided is a display panel including: a display area; and a gate driver to receive a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage to respectively apply a first gate voltage and a second gate voltage to the display area, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock bar signal, the first stage discharges the first gate voltage based on the first clock signal and a first transfer signal, and the second stage outputs the first transfer signal based on the second clock bar signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A display panel, comprising: a display area; and a gate driver configured to receive a plurality of clock signals comprising a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage, each of the first stage and the second stage configured to receive only one clock signal of the plurality of clock signals and respectively apply a first gate voltage and a…
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Classifications
Physics · mapped topic
- G09G3/3677Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9053677B2 cover?
- Provided is a display panel including: a display area; and a gate driver to receive a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage to respectively apply a first gate voltage and a second gate voltage to the display area, wherein the first clock signal and the first clock bar signal …
- Who is the assignee on this patent?
- Park Soo-Young, Wang In-Soo, Lee Gi-Chang, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G09G3/3677. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).