Trusted component update system and method

US9053323B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9053323-B2
Application numberUS-78687407-A
CountryUS
Kind codeB2
Filing dateApr 13, 2007
Priority dateApr 13, 2007
Publication dateJun 9, 2015
Grant dateJun 9, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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A trusted component update system comprises verify logic configured to validate integrity of an update to a trusted component of a computing device, and logic disposed in the trusted component and configured to validate integrity of the verify logic.

First claim

Opening claim text (preview).

What is claimed is: 1. A trusted component update system, comprising: a computing device comprising a hardware processing unit; verify logic stored in memory of the computing device and executed by the processing unit to validate integrity of an update to a trusted component of the computing device, the update to modify content of the trusted component; and logic stored in a boot block of trusted memory of the trusted component and executed by the processing unit to validate integrity of the verify logic before the verify logic validates the integrity of the update, wherein the update to the trusted component comprises an update to the boot block of trusted memory of the trusted component, wherein the boot block provides boot-up functionality to the computing device. 2. The system of claim 1 , wherein the logic in the trusted component is configured to hash at least a portion of the verify logic and compare the hash of the verify logic with a predetermined hash value stored in the boot block of trusted memory of the trusted component to validate the integrity of the verify logic. 3. The system of claim 1 , wherein the verify logic is configured to validate integrity of a signature associated with the update. 4. The system of claim 1 , wherein the verify logic is configured to hash at least a portion of the update and compare the hash of the update to a decrypted digital signature signed by a trusted party to validate the integrity of the update. 5. The system of claim 1 , wherein the boot block of the trusted component is configured to determine availability of the update upon booting of the computing device. 6. The system of claim 1 , wherein the trusted component comprises a firmware flash memory. 7. A trusted component update method, comprising: validating, by a hardware processing unit of a computing device, integrity of an update to a trusted component of the computing device using verify logic stored in memory of the computing device, the update to change existing contents of the trusted component; and before the validating of the integrity of the update, validating, by the processing unit of the computing device, integrity of the verify logic using logic stored in a boot block of trusted memory of the trusted component, wherein the update to the trusted component comprises an update to the boot block of trusted memory of the trusted component, wherein the boot block provides boot-up functionality to the computing device. 8. The method of claim 7 , wherein validating the integrity of the update comprises validating integrity of a signature associated with the update. 9. The method of claim 7 , wherein validating the integrity of the verify logic comprises hashing at least a portion of the verify logic and comparing the hash of the verify logic with a predetermined hash value stored in the boot block of trusted memory of the trusted component. 10. The method of claim 7 , wherein validating the integrity of the update comprises hashing at least a portion of the update and comparing the hash of the update to a decrypted digital signature signed by a trusted party. 11. The method of claim 7 , further comprising determining, by the boot block of the trusted component, availability of the update upon booting of the computing device. 12. The system of claim 1 , wherein the memory of the computing device comprises non-trusted system memory of the computing device. 13. The system of claim 1 , wherein the boot block of trusted memory resides in firmware memory of the trusted component. 14. The system of claim 1 , wherein the logic executed by the processing unit to validate integrity of the verify logic is stored in the boot block of trusted memory of the trusted component before the update is available. 15. The system of claim 1 , further comprising: boot instructions stored in the boot block of trusted memory of the trusted component. 16. The method of claim 7 , wherein the memory of the computing device comprises non-trusted system memory of the computing device. 17. The method of claim 7 , wherein the boot block of trusted memory resides in firmware memory of the trusted component.

Assignees

Inventors

Classifications

  • G06F21/572Primary

    Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

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Frequently asked questions

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What does patent US9053323B2 cover?
A trusted component update system comprises verify logic configured to validate integrity of an update to a trusted component of a computing device, and logic disposed in the trusted component and configured to validate integrity of the verify logic.
Who is the assignee on this patent?
Balacheff Boris, Ali Valiuddin Y, Wang Lan, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F21/572. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).