Method and apparatus for supporting a unified debug environment

Patent metadata

Field	Value
Publication number	US-9053232-B2
Application number	US-201213715161-A
Country	US
Kind code	B2
Filing date	Dec 14, 2012
Priority date	Dec 14, 2012
Publication date	Jun 9, 2015
Grant date	Jun 9, 2015

Abstract

A field programmable gate array (FPGA) includes a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA. The FPGA includes a system on a chip (SOC) that includes a hard processor and a hard processor debug unit. The FPGA includes a bus bridge, coupled to an input output (IO) of the FPGA, operable to transmit data between the IO and the soft processor debug unit and the hard processor debug unit.

First claim

What is claimed is:

1. A hybrid field programmable gate array (FPGA), comprising
a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA;
a system on a chip (SOC) that includes a hard processor and a hard processor debug unit; and
a bus bridge, coupled to an input output (IO) of the FPGA, that transmits data between the IO and the soft processor debug unit and the hard processor debug unit.

2. The hybrid FPGA of cla…

Assignees

• Altera Corp

Inventors

• Ahmed Muhammad
• Reghunath Manoj

Classifications

• G06F11/27

  Physics · mapped topic

• G06F11/3648 Primary

  Physics · mapped topic

• G06F11/3698

  Physics · mapped topic

• G06F11/3664

  Physics · mapped topic