Modular direct memory access system

Patent metadata

Field	Value
Publication number	US-9053093-B1
Application number	US-201313974682-A
Country	US
Kind code	B1
Filing date	Aug 23, 2013
Priority date	Aug 23, 2013
Publication date	Jun 9, 2015
Grant date	Jun 9, 2015

Abstract

One embodiment relates to an integrated circuit with a modular direct memory access system. A read data mover receives data obtained from a source address, and a write data mover for sends the data to a destination address. A descriptor controller provides the source address to the read data mover and the destination address to the write data mover. Another embodiment relates to a method of providing direct memory access. Another embodiment relates to a system which provides direct memory access. Other embodiments and features are also disclosed.

First claim

What is claimed is:

1. An integrated circuit with a modular direct memory access system, the integrated circuit comprising:
a read data mover for receiving data obtained from an original source address;
a write data mover for sending the data to a final destination address; and
a descriptor controller for providing the original source address to the read data mover and the final destination address to the write data mover,
wherein the descriptor controller comprises circuitry electronically programmed to cause the read data mover to copy a descriptor table from memory of a root complex to local memory in the integrated circuit, wherein the descriptor table includes at least one descriptor, and wherein said at least one descriptor comprises an original source address, a final destination address, and a length of the data.

2. The integrated circuit of claim 1 , wherein the read and write data movers are implemented in hard-wired circuitry, and wherein the descriptor controller is implemented in electronically-programmed circuitry.

3. The integrated circuit of claim 1 further comprising:
local memory;
a write data interface for writing data from the read data mover to the local memory; and
a read data interface for reading data from the local memory to the write data mover.

4. The integrated circuit of claim 1 , wherein the descriptor controller comprises circuitry electronically programmed to load at least one descriptor from the local memory in the integrated circuit, generate read and write descriptors from said at least one descriptor, provide the read descriptor to the read data mover, and provide the write descriptor to the write data mover.

5. The integrated circuit of claim 4 , wherein the descriptor controller further comprises circuitry electronically programmed to receive status messages from the read and write data movers.

6. An integrated circuit with a modular direct memory access system, the integrated circuit comprising:
a read data mover for receiving data obtained from an original source address;
a write data mover for sending the data to a final destination address;
a descriptor controller for providing the original source address to the read data mover and the final destination address to the write data mover;
a transmit slave interface;
a transmit interface; and
a transmit control module for receiving control messages from the descriptor controller via the transmit slave interface and transmitting the control messages to a root complex via the transmit interface.

7. The integrated circuit of claim 6 further comprising:
a transmit arbitrator for scheduling outgoing data paths from the read data mover, the write data mover, and the transmit control module, the transmit arbitrator providing an output to the transmit interface.

8. An integrated circuit with a modular direct memory access system, the integrated circuit comprising:
a read data mover for receiving data obtained from an original source address;
a write data mover for sending the data to a final destination address;
a descriptor controller for providing the original source address to the read data mover and the final destination address to the write data mover;
a receive interface;
a receive master interface; and
a receive control module for receiving control messages from a root complex via the receive interface and communicating the control messages to the descriptor controller via the receive master interface.

9. A method of providing a direct memory access (DMA) transfer using an integrated circuit, the method comprising:
obtaining a descriptor by a descriptor controller, wherein the descriptor comprises at least an original source address for the DMA transfer, a final destination address for the DMA transfer, and a data length;
reading data starting at the original source address by a read data mover;
writing the data by the read data mover to an end-point address in local memory on the integrated circuit;
reading the data from the end-point address in the local memory by a write data mover;
writing the data by the write data mover to the final destination address; and
the descriptor controller causing the read data mover to copy a descriptor table comprising a plurality of descriptors from memory of a root complex to the local memory on the integrated circuit.

10. The method of claim 9 , wherein the read and write data movers are implemented in hard-wired circuitry of the integrated circuit, and wherein the descriptor controller is implemented in electronically-programmed circuitry of the integrated circuit.

11. The method of claim 9 , wherein the descriptor controller comprises circuitry electronically programmed to load at least one descriptor from the local memory, generate read and write descriptors from said at least one descriptor, provide the read descriptor to the read data mover, and provide the write descriptor to the write data mover.

12. The method of claim 11 , wherein the descriptor controller comprises circuitry electronically programmed to receive status messages from the read and write data movers.

13. A system for direct memory access, the system comprising:
a root complex comprising a central processing unit, main memory, and a root port communicatively connected to the main memory and the central processing unit;
a read data mover for receiving data obtained from a source address;
a write data mover for sending the data to a destination address;
at least one descriptor controller for providing the source address to the read data mover and the destination address to the write data mover;
a data link communicatively interconnecting the root complex and the read and write data movers;
local memory;
a write data interface for writing data from the read data mover to the local memory; and
a read data interface for reading data from the local memory to the write data mover,
wherein the read and write data movers are implemented in hard-wired circuitry, and wherein the descriptor controller is implemented in electronically-programmed circuitry,
wherein the descriptor controller comprises circuitry electronically programmed to cause the read data mover to copy a descriptor table from memory of the root complex to the local memory, wherein the descriptor table includes at least one descriptor, and wherein said at least one descriptor comprises a source address, a destination address, and a length of the data.

14. The system of claim 13 , wherein the descriptor controller comprises circuitry electronically programmed to load at least one descriptor from the local memory and direct the read and write data movers to transfer data according to said at least one descriptor, and wherein said at least one descriptor comprises a source address, a destination address, and a length of the data.

15. The system of claim 14 , wherein the descriptor controller further comprises circuitry electronically programmed to receive status messages from the read and write data movers.

16. The system of claim 13 , wherein the system is in a single packaged device.

17. A system for direct memory access, the system comprising:
a root complex comprising a central processing unit, main memory, and a root port communicatively connected to the main memory and the central processing unit;
a read data mover for receiving data obtained from a source address;
a write data mover for sending the data to a destination address;
at least one descriptor controller for providing the source address to the read data mover and the destination address to the write data mover;

Assignees

• Altera Corp

Inventors

• Nguyen Harry
• Finan Christopher D
• Molson Philippe

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2213/2802

  DMA using DMA transfer descriptors · CPC title

• G06F9/30192

  according to data descriptor, e.g. dynamic data typing · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title