Data processor and control system

Patent metadata

Field	Value
Publication number	US-9052912-B2
Application number	US-201414242820-A
Country	US
Kind code	B2
Filing date	Apr 1, 2014
Priority date	Mar 8, 2007
Publication date	Jun 9, 2015
Grant date	Jun 9, 2015

Abstract

Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

First claim

What is claimed is:

1. A data processor comprising:
a central processing unit which executes an instruction;
a plurality of circuit modules used by the central processing unit;
a first controller which sends a request for interruption to the central processing unit in response to a generated event signal; and
a second controller which outputs a start control signal to each of the first controller and the plurality of circuit modules in response to a generated event signal.…

Assignees

• Renesas Electronics Corp

Inventors

• Oyama Hidemi
• Kawamura Masanobu
• Ikeguchi Takuya
• Matsumoto Masanori
• Kawajiri Hiroyuki

Classifications

• G06F9/3861

  Physics · mapped topic

• G06F13/24 Primary

  Physics · mapped topic

• G06F9/3865 Primary

  Physics · mapped topic