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US-2024045680-A1 · Feb 8, 2024 · US
Recovering from exceptions and timing errors
US9052909B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9052909-B2 |
| Application number | US-201113313053-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 7, 2011 |
| Priority date | Dec 7, 2011 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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- Title
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Abstract
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A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.
First claim
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We claim: 1. A data processing apparatus comprising a processing pipeline for processing a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said processing pipeline comprising: exception control circuitry; error detection circu…
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Frequently asked questions
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- What does patent US9052909B2 cover?
- A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicatin…
- Who is the assignee on this patent?
- Piry Frederic Claude Marie, Scalabrino Luca, Schon Guillaume, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/384. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).