System cache with coarse grain power management
US-9218040-B2 · Dec 22, 2015 · US
Idle power reduction for memory subsystems
US9052899B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9052899-B2 |
| Application number | US-201113206888-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 10, 2011 |
| Priority date | Aug 10, 2011 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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Abstract
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Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. Embodiments of the invention may comprise of logic, modules or any combination thereof, to detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards its respective memory unit(s), a processor core executing a processor low-power mode, and a processor socket (operatively coupling the processing core and the memory unit) executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit(s) and various components of the memory subsystem.
First claim
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The invention claimed is: 1. A system comprising: a multiple processor; a system memory unit, the system memory unit having a first memory region and a second memory region, the first memory region being architecturally closer to the multiple processors than the second memory region; a memory controller coupled to the first memory region to control data transferred to and from the second memory region; a memory power management module to help execute a low-power idle state e…
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Physics · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
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Frequently asked questions
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- What does patent US9052899B2 cover?
- Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. Embodiments of the invention may comprise of logic, modules …
- Who is the assignee on this patent?
- Thomas Tessil, Ganesan Baskaran, Dakshinamurthy Sampath, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F1/3225. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).