Memory performance when speculation control is enabled, and instruction therefor
US-2015378915-A1 · Dec 31, 2015 · US
Load pair disjoint facility and instruction therefor
US9052889B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9052889-B2 |
| Application number | US-201213726746-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 26, 2012 |
| Priority date | Feb 18, 2010 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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Abstract
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A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.
First claim
Opening claim text (preview).
What is claimed is: 1. A computer program product for executing a Load/Store Disjoint (LSD) instruction in a processor of a multi-processor system, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: obtaining a Load/Store Disjoint instruction for execution, the Load/Store Disjoint instruction comprising an opcode and specifying…
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- G06F9/3004Primary
Physics · mapped topic
Physics · mapped topic
- G06F9/30043Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9052889B2 cover?
- A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses ar…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3004. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).